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Tz50 Introduction
Tz50 Features
Tz50 Available Package Options
Tz50 Device Core Functional Description
Tz50 XLR Cell
Tz50 Embedded Memory
Tz50 True Dual-Port Mode
Tz50 Simple Dual-Port Mode
Tz50 DSP Block
Tz50 Clock and Control Network
Tz50 Clock Sources that Drive the Global and Regional Networks
Tz50 Driving the Global Network
Tz50 Driving the Regional Network
Tz50 Driving the Local Network
Tz50 Device Interface Functional Description
Tz50 Interface Block Connectivity
Tz50 GPIO
Tz50 Features for HVIO and HSIO Configured as GPIO
Tz50 Double-Data I/O
Tz50 Programmable Delay Chains
Tz50 HVIO
Tz50 HSIO
Tz50 HSIO Configured as GPIO
Tz50 HSIO Configured as LVDS
Tz50 HSIO Configured as MIPI Lane
Tz50 I/O Banks
Tz50 Oscillator
Tz50 PLL
Tz50 Dynamic Phase Shift
Tz50 Single-Event Upset Detection
Tz50 Internal Reconfiguration Block
Tz50 Security Feature
Tz50 Power Sequence
Tz50 Power-Up Sequence
Tz50 Power-Down Sequence
Tz50 Power Supply Current Transient
Tz50 Unused Resources and Features
Tz50 Configuration
Tz50 Supported FPGA Configuration Modes
Tz50 HyperRAM Characteristics
Tz50 Characteristics and Timing
Tz50 DC and Switching Characteristics
Tz50 HSIO Electrical and Timing Specifications
Tz50 PLL Timing and AC Characteristics
Tz50 Configuration Timing
Tz50 JTAG Mode
Tz50 SPI Active Mode
Tz50 SPI Passive Mode
Tz50 Pinout Description
Tz50 Configuration Pins
Tz50 Pin States
Tz50 Interface Floorplan
Tz50 Efinity Software Support
Tz50 Ordering Codes
Tz50 Revision History
Tz50
Ordering Codes
Refer to the
Topaz Selector Guide
for the full listing of
Tz50
ordering codes.