Tz50 Driving the Regional Network
The following figure shows the regional network clock sources graphically.
Note: The
figure shows the regional clock sources driven from the periphery; some FPGAs have additional regional buffers that can only be accessed
from the core. You use them by manually instantiating a
GBUFCE
primitive driven by the core and assigning it to the location of the
RBUFThe PLL CLKOUT4 can only connect to the top (or bottom) interface.
