Ti35 SPI Flash Memory

Ti35 FPGAs in the F100S3F2 package include a SPI flash memory. The SPI flash memory has a density of 16 Mbits and a clock rate of up to 85 MHz. You can fit two compressed bitstream images into the SPI flash.

Important: You cannot enable the Ti35 FPGA security features when using compressed bitstreams.

In SPI active configuration mode, the FPGA is configured using a bitstream stored in the SPI flash device. During configuration, the maximum clock frequency for the flash device is specified in Ti35 SPI Active Mode. When the FPGA is in user mode, you can access the flash at the flash device's maximum clock frequency (although different SPI flash commands may have different maximum clock frequencies).

Figure 1. Connections between FPGA and SPI Flash inside the Package
Important: The SPI flash memory's VCC is connected to VCCIO1A_4B. If you are using the SPI flash memory, drive the VCCIO1A_4B with a 1.8 V supply.
Table 1. SPI Flash Memory Signals (Interface to FPGA Fabric)
SPI Name Signal Direction Description
SCLK SCLK_OUT Input Clock output from FPGA CCK pin to SPI flash memory.
SCLK_OE Input Output enable. Required for multiple controller.
MOSI MOSI_IN Output Required for ×2 or ×4 data width.
MOSI_OUT Input Data output from FPGA CDI0 to SPI flash memory.
MOSI_OE Input Output enable. Required for ×2 data width, ×4 data width, or multiple controller.
MISO MISO_IN Output Data input to FPGA CDI1 from SPI flash memory.
MISO_OUT Input Required for ×2 or ×4 data width.
MISO_OE Input Output enable. Required for ×2 or ×4 data width.
WP_N WP_N_IN Output Required for ×4 data width.
WP_N_OUT Input Data output from FPGA CDI2 pin to SPI flash memory.
WP_N_OE Input Output enable. Required for ×4 data width or multiple controller.
HOLD_N HOLD_N_IN Output Required for ×4 data width.
HOLD_N_OUT Input Data output from FPGA CDI3 pin to SPI flash memory
HOLD_N_OE Input Output enable. Required for ×4 data width or multiple controller.
CS_N CS_N_OUT Input Chip select output from FPGA SSL_N pin to SPI flash memory.
CS_N_OE Input Output enable. Required for multiple controller.
CLK CLK Input Required for register interface.
To program the SPI flash memory, use one of these modes:
  • SPI Active using JTAG Bridge mode
  • SPI Active mode
Notice: Refer to the AN 033: Configuring Titanium FPGAs for information on programming the SPI flash memory.

The GPIOL_P_01 (SSL_N), GPIOB_P_26 (CCK), GPIOB_N_27 (CDI0), and GPIOB_P_27 (CDI1) resources are for the SPI active interface. You can use these signals to read/write user data to/from the SPI flash memory while the Ti35 FPGA is in user mode. You enable this feature by adding the SPI flash block to your interface design. These resources are not available as user I/O pins if you use the SPI flash block.

You can also write a new bitstream to the SPI flash memory by controlling the SPI signals with an external controller. In this case, the CRESET_N signal should stay low and the FPGA remains in reset mode, even though you stored a new bitstream in the SPI flash memory. To enable this mode, turn on Configuration > External Flash Control > Enable external controller acccess to flash memory in the Interface Designer.

Important: Refer to the "SPI Flash Interface" chapter in the Titanium Interfaces User Guide for instructions on using the SPI flash block.