Ti35 Dynamic Phase Shift

Ti35 FPGAs support a dynamic phase shift where you can adjust the phase shift of each output dynamically in user mode by up to 3.5 F_PLL cycles. For example, to phase shift a 400 MHz clock by 90-degree, configure the PLL to have a F_PLL frequency of 800 MHz, set the output counter division to 2, and set SHIFT[2:0] to 001.

Implementing Dynamic Phase Shift

Use these steps to implement the dynamic phase shift:

1. Write the new phase setting into SHIFT[2:0].
2. After one clock cycle of the targeted output clock that you want to shift, assert the SHIFT_SEL[n] and SHIFT_ENA signals.
3. Hold SHIFT_ENA and SHIFT_SEL[n] high for a minimum period of four clock cycles of the targeted output clock.
4. De-assert SHIFT_ENA and SHIFT_SEL[n]. Wait for at least four clock cycles of the targeted output clock before asserting SHIFT_ENA and SHIFT_SEL[n] again.

Note: n in SHIFT_SEL[n] represents the output clock that you intend to add phase shift.

The following waveforms describe the signals for a single phase shift and consecutive multiple phase shifts.