Ti35 Revision History

Corrected order of RBUF pins on the left and right in Ti35 Driving the Regional Network. (DOC-2783)

The Efinity software issues a warning (not error) if you do not leave enough separation between GPIO and LVDS or MIPI lane pins (see note). (DOC-2833)

Added pull-down resistor to HVIO figure Figure 1. (DOC-2884)

Corrected Figure 1 and Figure 5; they incorrectly showed two PLLs. (DOC-2932)

Updated Figure 4; some N signals were incorrectly labeled as P. (DOC-2676)

Updated Figure 1 due to incorrectly labeled buffers.

Updated NSTATUS in Table 2.

Added details about the maximum clock rate for the SPI flash device in F100S3F2 packages.

Fix typo in Ti35 Available Package Options. (DOC-2613)

Updated configuration timing and fuse programming waveforms. (DOC-2272)

In Table 2, updated "When Configured As" column for Sub-LVDS and SLVS. (DOC-2314)

Fixed typo in Table 2. (DOC-2038)

Changed column name from Pins to Configuration Functions in Table 2. (DOC-2038)

Added note after Table 2 directing the reader to the pinout file. (DOC-2038)

Updated Fuse Programming Requirements with details of VQPS current. (DOC-1999)

Added automotive grade to features. (DOC-1902)

Clarified which signals are available when LVDS settings are enabled. (DOC-1908)

Added reset recommendations for PLLs and cascaded PLLs. (DOC-1900)

Clarified how to program the SPI flash memory for F100S3F2 packages. (DOC-1792)

Added notes to the configuration timing and security feature topics about not using SPI and JTAG at the same time. (DOC-2047)

Updated configuration timing and fuse programming waveforns. (DOC-2156)

Clarified HVIO and HSIO pin states during configuration and when unused in user mode. (DOC-2041)

Security features are updated for F100S3F2 and F225 packages. (DOC-1867)

Added F100 and F256 packages. (DOC-1594)

Added EXTFB to table of alternate pin functions.

Corrected OUTCLK connection in Figure 1. (DOC-1630)

Rearranged Ti35 Configuration Timing to keep waveforms together with tables.

For the PLL equation F_VCO = (F_PFD x M x O x C_FBK ), removed the restriction that (M x O x C_FBK) must be ≤ 255.

Updated Ti35 Configuration Pins.

Added 1.35 V support.

Corrected block RAM count. (DOC-1685)

F100S3F2 supports SPI active x4 mode. (DOC-1707)

Removed table Single-Ended I/O and Dedicated Configuration Pins Schmitt Trigger Buffer Characteristic. Added 3.3 V and 2.5 V in table HSIO Pins Configured as Single-Ended I/O DC Electrical Characteristics. Added table Supported HVIO Drive Strength and Supported HSIO Drive Strength. (DOC-1377)

Updated min ramp time in table Power Supply Ramp Rates. (DOC-1407)

Updated CRESET_N requirement during power-up sequence. (DOC-1443)

Corrected typo for VCCIO33 max supply in Absolute Maximum Ratings table. (DOC-1483)

Added max. value of f_TCK at 3 MHz at an operating voltage of 1.8 V to in JTAG Mode table. Added max.value of V_IL at 0.28 V for 1.8 V JTAG Configuration in HVIO DC Electrical Characteristics. (DOC-1510 & ADV-2311-001)

Corrected typo in HSIO Pins Configured as Differential SSTL I/O Electrical Characteristics table. (DOC-1514)

Updated power-up sequence.

Updated initial CCK waveform of figure SPI Passive Mode (x1) Timing Sequence.

Updated Programmable Delay Chains section, and added static and dynamic delay step size specs. (DOC-1342)

Added note about keeping both the current and the next clocks toggling during dynamic clock switching. (DOC-1405)

Added note about 7 x 6 Quad mode output is truncated to 12-bit (DOC-1295)

Added slvs option for HSIO configured as LVDS blocks. (DOC-1190)

Updated SPI Flash Memory port list. (DOC-1296)

Updated 2.5 V LVCMOS max toggle rate. (DOC-1251)

Replaced t_{LVDS_DT} and t_INDT specs with t_{PLL_HLW} and t_{LVDS_CPA}. (DOC-1189)

Updated PLL LOCKED signal description. (DOC-1208)

Added LVDS RX DBG signals. (DOC-1124)

Added note about using LVDS blocks from the same side of the FPGA to minimize skew. (DOC-1150)

Updated PLL RSTN signal description about de-asserting only when CLKIN is stable. (DOC-1226)

Standardized VCCA pin names. (DOC_1114)

Added note about achieving maximum toggle rate. (DOC-1099)

Added link in Power Up Sequence pointing to the Web Interactive Hardware Design Checklist and Guidelines. (DOC-1123)

Updated REF_RES_3A pin connection requirement in the Pinout Description topic.

Updated configuration pins external weak pull-up requirements. (DOC-1035)

Added DPA specs and updated DPA description to support full-rate serialization mode only. (DOC-1078)

Updated LVDS and sub-LVDS specs to include half-rate and full-rate serialization. (DOC-1078)

Updated JTAG configuration timing specs. (DOC-1083)

Updated REF_RES_xx pins connection requirement. (DOC-943)

Corrected MIPI RX Lane Block Diagram. (DOC-878)

Removed GCTRL and RCTRL. (DOC-895)

Added note recommending up to only 2 cascading PLLs. (DOC-931)

Updated description about differential receivers are powered by VCCAUX. (DOC-929)

Removed footnote in Minimum Power Supply Current Transient table. (DOC-818)

Corrected SSU_N pin direction.

Added note about I/O availability when enabling SPI flash memory access during user mode for F100S3F2 packages. (DOC-824)

Updated I/O Banks by Package table.

Corrected available single-ended HSIO for W64 package.

Updated test condition load to maximum load in Maximum Toggle Rate Table. (DOC-781)

Corrected description for differential TX static programmable delay. (DOC-786)

Added notes about VCC requirements in SPI flash memory and HyperRAM for F100S3F2 packages. (DOC-773)

Added PLL period jitter spec with noisy input clock specs and updated test condition note. (DOC-771)

Updated HyperRAM clock rate and double data rate speed. (DOC-793)

Updated figure title for Connections for Clock and RX Data Lane in the Same MIPI RX Group. (DOC-739)

Updated LVDS/RSDS/mini-LVDS RX supported VCCIO. (DOC-740)

Updated Power Supply Current Transient and power sequence. (DOC-761)

Corrected RD and RST signal directions in MIPI RX Lane Block Diagram.

Updated power supply ramp rate and power up sequence diagram. (DOC-631)

Updated external pull-up requirement for dual-purpose configuration pins. (DOC-734)

Updated active and passive configuration timing specs. (DOC-708)

Update 2.5 V LVCMOS V_IH and V_IL specs. (DOC-718)

Added I_IN and V_IN specs. (DOC-652)

Updated and improved clock and control network content and figures. (DOC-668)

Updated MIPI and LVDS maximum toggle rate.

Added note about the block RAM content is random and undefined if it is not initialized. (DOC-729)

Added Schmitt Trigger input buffer specs. (DOC-606)

Added PLL reference clock input duty cycle specs. (DOC-661)

Updated HVIO maximum toggle rate specs. (DOC-689)

Removed I4 and I4L speed grades. (DOC-681)

Updated global clock buffer, DSP, BRAM, HSIO as LVDS, and HSIO as MIPI lane specs. (DOC-693)

Added internal weak pull-up resistor and drive strength specs for CDONE and CRESET_N. (DOC-635)

Added ambient storage temperature spec. (DOC-678)

Added Ordering Codes topic. (DOC-637)

Added SRL8 resource number. (DOC-596)

Added global clock buffer block characteristics. (DOC-577)

Updated power up sequence, updated power supply ramp rates, updated tCRESET_N and added power supply current transient specs. (DOC-643)

Added internal weak pull-up and pull-down specs for HVIO and HSIO. (DOC-561)

Updated the SHIFT[2:0] description in PLL Signals table and Dynamic Phase Shift topic. (DOC-570)

Updated note about leaving unassigned pins when using HSIO as GPIO, LVDS, or MIPI lanes. (DOC-581)

Updated the Security Feature topic. (DOC-538)

Added a note in the Single Event Upset Detection topic referring to the Titanium Interfaces User Guide for details on using this feature.

Updated LVDS standard compliance which is TIA/EIA-644. (DOC-592)

Updated F100 package name to F100S3F2. (DOC-593)

Updated the Security Feature topic.

Updated DIV 2 active mode f_{MAX_M} typical and maximum values. (DOC-509)

Added F_PLL specs and updated the PLL block diagram to include F_PLL. (DOC-512)

Added note stating that all PLL outputs lock on the negative clock edge. (DOC-511)

Updated sub-LVDS maximum toggle rate. (DOC-541)

Added description about CLKOUT0 limitation. (DOC-533)

Updated HyperRAM double-data rates to up to 500 Mbps. (DOC-554)

Added connection requirements for unused resources in Power Up Sequence topic.