Ti35 Clock Sources that Drive the Global and Regional Networks
The Ti35 global and regional networks are highly flexible and configurable. Clock sources can come from interface blocks, such as GPIO or PLLs, or from the core fabric.
| Source | Description |
|---|---|
| GPIO | Supports GCLK and RCLK. (Only the P resources support this connection type). |
| LVDS RX | Supports GCLK and RCLK. |
| MIPI RX Lane (configured as clock lane) | Supports GCLK (default) and RCLK. You can only use resources that are identified as clocks. |
| PLL | Output clocks 0 - 3 connect to the global network.
Output clock 4 only connects to the regional network in the
top or bottom interface regions (depending on the location of
the PLL) and can only drive interface blocks on the top or
bottom of the FPGA.
Refer to Ti35 Driving the Regional Network for the PLL clocks that drive the regional network. |
| Oscillator | Connects to global buffer. |
| Core | Signals from the core logic can drive the global or regional network. |