Efinix, Inc.
  • Ti35 Introduction
  • Ti35 Features
    • Ti35 Available Package Options
  • Ti35 Device Core Functional Description
    • Ti35 XLR Cell
    • Ti35 Embedded Memory
      • Ti35 True Dual-Port Mode
      • Ti35 Simple Dual-Port Mode
    • Ti35 DSP Block
    • Ti35 Clock and Control Network
      • Ti35 Clock Sources that Drive the Global and Regional Networks
      • Ti35 Driving the Global Network
      • Ti35 Driving the Regional Network
      • Ti35 Driving the Local Network
  • Ti35 Device Interface Functional Description
    • Ti35 Interface Block Connectivity
    • Ti35 GPIO
      • Ti35 Features for HVIO and HSIO Configured as GPIO
        • Ti35 Double-Data I/O
        • Ti35 Programmable Delay Chains
      • Ti35 HVIO
      • Ti35 HSIO
        • Ti35 HSIO Configured as GPIO
        • Ti35 HSIO Configured as LVDS
        • Ti35 HSIO Configured as MIPI Lane
      • Ti35 I/O Banks
    • Ti35 Oscillator
    • Ti35 PLL
      • Ti35 Dynamic Phase Shift
    • Ti35 SPI Flash Memory
    • Ti35 HyperRAM Interface
    • Ti35 Single-Event Upset Detection
    • Ti35 Internal Reconfiguration Block
  • Ti35 Security Feature
  • Ti35 Power Sequence
    • Ti35 Power-Up Sequence (No VQPS)
    • Ti35 Power-Up Sequence (VQPS)
    • Ti35 Power-Down Sequence
    • Ti35 Power Supply Current Transient
    • Ti35 Unused Resources and Features
  • Ti35 Configuration
    • Ti35 Supported FPGA Configuration Modes
  • Ti35 Characteristics and Timing
    • Ti35 DC and Switching Characteristics
    • Ti35 HSIO Electrical and Timing Specifications
    • Ti35 PLL Timing and AC Characteristics
    • Ti35 HyperRAM Characteristics
    • Ti35 Configuration Timing
      • Ti35 JTAG Mode
      • Ti35 SPI Active Mode
      • Ti35 SPI Passive Mode
  • Ti35 Pinout Description
    • Ti35 Configuration Pins
    • Ti35 Pin States
  • Ti35 Interface Floorplan
  • Ti35 Efinity Software Support
  • Ti35 Ordering Codes
  • Ti35 Revision History

Ti35 Power Sequence

Important: You must follow the power-up and power-down sequence when powering Titanium FPGAs.
  • Ti35 Power-Up Sequence (No VQPS)
  • Ti35 Power-Up Sequence (VQPS)
  • Ti35 Power-Down Sequence
  • Ti35 Power Supply Current Transient
  • Ti35 Unused Resources and Features

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