Ti35 Pin States

HVIO pins have an internal pullup/down (see Figure 1); HSIO configured as GPIO have an internal pull up/down (see Figure 1). The following table shows the pin state during reset, configuration, and when unused in user mode.

Note: For the DDR pin states, refer to the Titanium DDR DRAM Block User Guide.

Table 1. I/O Pin States
Pin Type	During Reset (CRESET_N Low)	During Configuration (CRESET_N High, CDONE Low)	When Unused in User Mode (Default)
User Pins
HSIO	Input tri-state with weak pull up.	Input tri-state with weak pull up.	Input tri-state with weak pull up.^¹
HVIO	Input tri-state with weak pull up.	Input tri-state with weak pull up.	Input tri-state with weak pull up.^¹
Dual-Purpose Configuration Pins
CSO	0	0²	Input tri-state with weak pull up.
NSTATUS	0	1³	Input tri-state with weak pull up.
CCK	Input tri-state with weak pull up.	SPI active output clock. SPI passive input with weak pull up.	Input tri-state with weak pull up.
CDI0	Input tri-state with weak pull up.	SPI active output. SPI passive input with weak pull up.	Input tri-state with weak pull up.

As shown in Ti35 Power-Up Sequence (VQPS) and Ti35 Power-Up Sequence (No VQPS), CRESET_N must be kept low during power up.

Note: Refer to the following tables for details:

Table 14

Table 15

¹ You can change the default mode to weak pull-down in the Interface Designer.

² CSO is driven to 1 when the bitstream is done transmitting.

³ NSTATUS set to 1 if valid bit stream detected. Remains at 0 if bit stream is authenticated or encrypted.