• Ti135 Data Sheet: Introduction
  • Ti135 Features
    • Ti135 Available Package Options
  • Ti135 Device Core Functional Description
    • Ti135 XLR Cell
    • Ti135 Embedded Memory
      • Ti135 True Dual-Port Mode
      • Ti135 Simple Dual-Port Mode
    • Ti135 DSP Block
    • Ti135 Clock and Control Network
      • Ti135 Clock Sources that Drive the Global and Regional Networks
      • Ti135 Driving the Global Network
      • Ti135 Driving the Regional Network
      • Ti135 Driving the Local Network
  • Ti135 Device Interface Functional Description
    • Ti135 Interface Block Connectivity
    • Ti135 GPIO
      • Ti135 Features for HVIO and HSIO Configured as GPIO
        • Ti135 Double-Data I/O
        • Ti135 Programmable Delay Chains
      • Ti135 HVIO
      • Ti135 HSIO
        • Ti135 HSIO Configured as GPIO
        • Ti135 HSIO Configured as LVDS
        • Ti135 HSIO Configured as MIPI Lane
      • Ti135 I/O Banks
    • Ti135 DDR DRAM Interface
    • Ti135 LPDDR4/4x SDRAM (N576D2F4 and N576D3F4 Only)
    • Ti135 MIPI D-PHY
      • Ti135 MIPI RX D-PHY
      • Ti135 MIPI TX D-PHY
    • Ti135 Oscillator
    • Ti135 Fractional PLL
      • Ti135 Reference Clock Resource Assignments
      • Ti135 Programmable Duty Cycle
      • Ti135 Fractional Output Divider
      • Ti135 Spread-Spectrum Clocking
      • Ti135 Dynamic PLL Reconfiguration
      • Ti135 Dynamic Phase Shift
    • Ti135 Spread-Spectrum Clocking PLL
    • Ti135 Hardened RISC-V Block Interface
    • Ti135 SPI Flash Memory
    • Ti135 Transceiver Interface
    • Ti135 Single-Event Upset Detection
    • Ti135 Internal Reconfiguration Block
  • Ti135 Security Feature
  • Ti135 Power Sequence
    • Ti135 Power-Up Sequence
    • Ti135 LPDDR4/4x SDRAM Power Up Requirements
    • Ti135 Power-Down Sequence
    • Ti135 Power Supply Current Transient
    • Ti135 Unused Resources and Features
  • Ti135 Configuration
    • Ti135 Supported Configuration Modes
  • Ti135 Characteristics and Timing
    • Ti135 DC and Switching Characteristics
    • Ti135 HSIO Electrical and Timing Specifications
    • Ti135 MIPI Electrical Specifications and Timing
      • Ti135 MIPI Reset Timing
    • Ti135 PLL Timing and AC Characteristics
    • Ti135 Configuration Timing
      • Ti135 JTAG Mode
      • Ti135 SPI Active Mode
      • Ti135 SPI Passive Mode
    • Ti135 Transceiver Specifications
  • Ti135 Pinout Description
    • Ti135 Configuration Pins
    • Ti135 Dedicated DDR Pinout
    • Ti135 Dedicated MIPI D-PHY Pinout
    • Ti135 Dedicated Transceiver Pinout
    • Ti135 Pin States
  • Ti135 Interface Floorplan
  • Ti135 Efinity Software Support
  • Ti135 Ordering Codes
  • Ti135 Revision History

Ti135 Characteristics and Timing

The following table shows the specification status for Ti135 packages.

Table 1. Package Status
Package Status
N441, N484 (Q3 speed grades), N576, N576D2F4, N576D3F4 Preliminary
N484 (all other speed grades), N676 Final
  • Ti135 DC and Switching Characteristics
  • Ti135 HSIO Electrical and Timing Specifications
  • Ti135 MIPI Electrical Specifications and Timing
  • Ti135 PLL Timing and AC Characteristics
  • Ti135 Configuration Timing
  • Ti135 Transceiver Specifications