Ti135 Configuration Pins

Table 1. Dedicated Configuration PinsThese pins cannot be used as general-purpose I/O after configuration.
All the pins are in internal weak pull-up during configuration mode except for TCK and TDO.
Calculate the resistor value as described in "Resistors in Configuration Circuitry" in AN 033: Configuring Titanium FPGAs.
Pins Direction Description External Weak Pull Up/Pull Down Requirement
CDONE I/O Configuration done status pin. CDONE is an open drain output; connect it to an external pull-up resistor to VCCIO. When CDONE = 1, the configuration is complete and the FPGA enters user mode. You can hold CDONE low and release it to synchronize the FPGAs entering user mode. Pull up
CRESET_N Input Active-low FPGA reset and re-configuration trigger.
Pulse CRESET_N low for a duration of tcreset_N before releasing CRESET_N from low to high to initiate FPGA re-configuration. This pin does not perform a system reset.
 Pull up
TCK Input JTAG test clock input (TCK). The rising edge loads signals applied at the TAP input pins (TMS and TDI). The falling edge clocks out signals through the TAP TDO pin. Pull up
TMS Input JTAG test mode select input (TMS). The I/O sequence on this input controls the test logic operation . The signal value typically changes on the falling edge of TCK. TMS is typically a weak pull-up; when it is not driven by an external source, the test logic perceives a logic 1. Pull up
TDI Input JTAG test data input (TDI). Data applied at this serial input is fed into the instruction register or into a test data register depending on the sequence previously applied at TMS. Typically, the signal applied at TDI changes state following the falling edge of TCK while the registers shift in the value received on the rising edge. Like TMS, TDI is typically a weak pull-up; when it is not driven from an external source, the test logic perceives a logic 1. Pull up
TDO Output JTAG test data output (TDO). This serial output from the test logic is fed from the instruction register or a test data register depending on the sequence previously applied at TMS. The shift out content is based on the issued instruction. The signal driven through TDO changes state following the falling edge of TCK. When data is not being shifted through the device, TDO is set to an inactive drive state (e.g., high-impedance). Pull up
JTAG_VCCIO_SEL Input JTAG voltage select pin.
This pin affects the voltage for the bank in which it is located (BR1), or any banks merged with it. Supply VCCIO33_BR1 with 1.8 V and connect a 1 kΩ external resistor between this pin and ground to use JTAG at 1.8 V.
Leave this pin floating to use the default JTAG at 3.3 V or 2.5 V.
Floating or pull down
Table 2. Dual-Purpose Configuration PinsIn user mode (after configuration), you can use these dual-purpose pins as general I/O. Calculate the resistor value as described in "Resistors in Configuration Circuitry" in AN 033: Configuring Titanium FPGAs.
Configuration Functions Direction Description External Weak Pull Up/Pull Down Requirement
CBSEL[1:0] Input Multi-image configuration selection pin. This function is not applicable to single-image bitstream configuration or internal reconfiguration (remote update).
Connect CBSEL[1:0] to the external resistors for the image you want to use:
00 for image 1
01 for image 2
10 for image 3
11 for image 4
0: Connect to an external weak pull down.
1: Connect to an external weak pull up.
 Pull up or pull down
CCK I/O Passive SPI input configuration clock or active SPI output configuration clock. Optional pull up if required by external load
CDIn I/O Data input for SPI configuration. n is a number from 0 to 31 depending on the SPI configuration data width.
CDI0 is an output in x1 active configuration mode and is a bidirectional pin in all other active configuration modes.
CDI4 is a bidirectional pin in x8 active configuration mode.
In a multi-bit daisy chain connection, CDI[31:0] connects to the data bus in parallel.
 Optional pull up if required by external load
CSI Input Chip select.
0: The FPGA is not selected or enabled and will not be configured.
1: Select the FPGA for configuration modes.
CSI must remain high throughout configuration.
 Pull up
CSO Output Chip select output. Asserted after configuration is complete. Connect this pin to the chip select pin of the next FPGA for daisy chain configuration. –
NSTATUS Output
Indicates a configuration error. When the FPGA drives this pin low, it indicates either a device mismatch or a failed bitstream CRC check. Refer to Table 1.
 –
SSL_N I/O
SPI configuration mode select. The FPGA senses the value of SSL_N when it comes out of reset (i.e., CRESET_N transitions from low to high).
0: Passive mode; connect to external weak pull down.
1: Active mode; connect to external weak pull up.
In active configuration mode, SSL_N is an active-low chip select to the flash device (CDI0 - CDI3).
 Pull up or pull down
SSU_N Output Active-low chip select to the upper flash device (CDI4 - CDI17) in active x8 configuration mode (dual quad mode). Optional pull up if required by external load
EXT_CONFIG_CLK Input Alternative clock in active configuration mode. Optional pull up if required by external load
TEST_N Input Active-low test mode enable signal. Set to 1 to disable test mode.
During all configuration modes, rely on the external weak pull-up or drive this pin high.
Pull up
Note: Refer to the column Configuration Functions in the pinout file.
1 CDONE has a drive strength of 12 mA at 1.8 V.