Ti135 Revision History

CDI17 corrected as CDI7 in dedicated configuration pin description for SSU_N. (DOC-3074)

Corrected the GPIO or LVDS global clock resources on the right side for Figure 1. (DOC-3060)

Characteristics and timing for N676 package are final. (DOC-3001)

Characteristics and timing for N484 package are final (except Q3 speed grades). (DOC-3280)

Updated transceiver specifications. (DOC-2974, DCO-3045)

Added initial pin state information and absolute maximum ratings for transceiver pins. (DOC-2974)

Removed incorrect instruction about turning on an external controller to the SPI flash topic. (DOC-3095)

The LPDDR4/4x memory in the N576D2F4 and N576D3F4 packages supports speeds up to 3,500 Mbps for LPDDR4x and 3,300 Mbps for LPDDR4. (DOC-3175)

Added the power-down sequence for the LPDDR4/4x in N576D2F4 and N576D3F4 packages. (DOC-3071)

Added N576D3F4 package. (DOC-3235)

Corrected packages in Table 21 and Table 22. (DOC-2877)

Updated the VDDQ recommended operating conditions. (DOC-2881)

Corrected AXI interrupt signal direction in Hardened RISC-V Block Diagram. (DOC-2885)

Added pull-down resistor to HVIO figure Figure 1. (DOC-2884)

Added transceiver analog power supply (VDDA_H_Q) specification. (DOC-2910)

Corrected Figure 1 and Figure 5; they incorrectly showed two PLLs. (DOC-2932)

Added transceiver reference clock to Ti135 Power-Up Sequence. (DOC-2947)

Added PCIe Gen4 support for N441 packages. (DOC-2724)

Q3 speed added in tables. (DOC-2737)

Updated Table 2.

Revised Table 2 for added clarity.

Added N576 and N576D2F4 packages. (DOC-2640)

Updated PLL maximum locked time in Table 2 (DOC-2468)

Update number of core regional networks in Ti135 Clock and Control Network. (DOC-2473)

Added N441 package information.

Added Ti135 Transceiver Specifications. (DOC-2282)

Updated JTAG_VCCIO_SEL voltage in Table 1. (DOC-2558)

Added N484 package information. (DOC-2260)

Updated configuration timing and fuse programming waveforms. (DOC-2272)

Moved table describing connection requirements for unused resources and features to the Ti135 Unused Resources and Features topic.

Updated differential I/O programmable delay chain step size specification. (DOC-2351)

In Table 2, updated "When Configured As" column for Sub-LVDS and SLVS. (DOC-2314)

Added RISC-V memory clock speed to ref_dc_switch_ti60.html#ref_dc_switch_t20__table_q3p_jsj_hsb. (DOC-2278)

Fixed typo in Table 2. (DOC-2038)

Changed column name from Pins to Configuration Functions in Table 2. (DOC-2038)

Added note after Table 2 directing the reader to the device pinout file. (DOC-2038)

July 2024