Ti135 Power-Down Sequence

There is no specific power-down sequence for Ti135 FPGAs. However, the VQPS power supply must follow the specifications in Fuse Programming Requirements.

For packages with a LPDDR4/4x device, refer to the following figure for the power-down sequence.

Figure 1. LPDDR4/4x Power-Down Sequence

When the FPGA begins to power off:

  1. The CRESET_N signal drops to VIL to reset the LPDDR4/4x hard controller, releasing CKE to tri-state.
  2. VDD2 and VDDQ power down.
  3. VDD1 powers down; VDD1, VDD2, and VDDQ are below 300 mV.
VDD1 and VDD2 must decrease with a slope lower than 0.5V/μS between Tx and Tz. Refer to the LPDDR4/4x device data sheet for the Tx and Tz power supply specifications.
Notice: Refer to the LPDDR4/4x device's data sheet for the power-down details. See the Documentation page on the Support Center for the data sheet links.