T20 Global Clock Location (W80, Q100F3, Q144, F169, and F256)

Table 1. Left Clock Input from GPIO Pins

Function Name	Resource Name	GCLK[0]	GCLK[1]	GCLK[2]	GCLK[3]	GCLK[4]	GCLK[5]	GCLK[6]	GCLK[7]
CLK0	GPIOL_24		–	–	–		–	–	–
CLK1	GPIOL_25	–		–	–	–		–	–
CLK2	GPIOL_26	–	–		–	–	–		–
CLK3	GPIOL_27	–	–	–		–	–	–
CLK4	GPIOL_28		–	–	–		–	–	–
CLK5	GPIOL_29	–		–	–	–		–	–
CLK6	GPIOL_30	–	–		–	–	–		–
CLK7	GPIOL_31	–	–	–		–	–	–

Table 2. Left Clock from PLL OUTCLK Signal

PLL Reference	CLKOUT	GCLK[0]	GCLK[1]	GCLK[2]	GCLK[3]	GCLK[4]	GCLK[5]	GCLK[6]	GCLK[7]
PLL_TL0	CLKOUT0		–	–	–	–	–		–
	CLKOUT1	–			–	–	–	–	–
	CLKOUT2	–			–	–	–	–	–
PLL_TL1	CLKOUT0	–	–	–		–	–	–
	CLKOUT1	–	–	–	–			–	–
	CLKOUT2	–	–	–	–			–	–

Table 3. Right Clock Input from GPIO Pins

Function Name	Resource Name	GCLK[8]	GCLK[9]	GCLK[10]	GCLK[11]	GCLK[12]	GCLK[13]	GCLK[14]	GCLK[15]
CLK0	GPIOR_127		–	–	–		–	–	–
CLK1	GPIOR_126	–		–	–	–		–	–
CLK2	GPIOR_125	–	–		–	–	–		–
CLK3	GPIOR_124	–	–	–		–	–	–
CLK4	GPIOR_123		–	–	–		–	–	–
CLK5	GPIOR_122	–		–	–	–		–	–
CLK6	GPIOR_121	–	–		–	–	–		–
CLK7	GPIOR_120	–	–	–		–	–	–

Table 4. Right Clock from PLL OUTCLK Signal

PLL Reference	CLKOUT	GCLK[8]	GCLK[9]	GCLK[10]	GCLK[11]	GCLK[12]	GCLK[13]	GCLK[14]	GCLK[15]
PLL_TR0	CLKOUT0		–	–	–	–	–		–
	CLKOUT1	–			–	–	–	–	–
	CLKOUT2	–			–	–	–	–	–
PLL_TR1	CLKOUT0	–	–	–		–	–	–
	CLKOUT1	–	–	–	–			–	–
	CLKOUT2	–	–	–	–			–	–
PLL_BR0	CLKOUT0		–	–	–	–	–	–
	CLKOUT1	–			–	–	–	–	–
	CLKOUT2	–			–	–	–	–	–