T20 Interface Floorplans

Note: The numbers in the floorplan figures indicate the GPIO and LVDS number ranges. Some packages may not have all GPIO or LVDS pins in the range bonded out. Refer to the T20 Pinout for information on which pins are available in each package.

Figure 1. Floorplan Diagram for FPGAs in W80 Packages (with MIPI)

Figure 2. Floorplan Diagram for Q100F3 and Q144 Packages

Figure 3. Floorplan Diagram for FPGAs in F169 Packages (with MIPI)

Figure 4. Floorplan Diagram for FPGAs in F256 Packages

Figure 5. Floorplan Diagram for FPGAs in F324 Packages (with DDR and MIPI)

Figure 6. Floorplan Diagram for FPGAs in F400 Packages (with DDR)