T20 LVDS I/O Electrical and Timing Specifications

The LVDS pins comply with the EIA/TIA-644 electrical specifications.

Note: The LVDS RX supports the sub-lvds, slvs, HiVcm, RSDS and 3.3 V LVPECL differential I/O standards with a transfer rate of up to 800 Mbps.

Table 1. LVDS I/O Electrical Specifications
Parameter	Description	Test Conditions/Options	Min	Typ	Max	Unit
V_CCIO	LVDS I/O Supply Voltage	–	2.97	3.3	3.63	V
LVDS TX
V_OD	Output Differential Voltage	Reduce VOD Swing option disabled	250	350	450	mV
V_OD	Output Differential Voltage	Reduce VOD Swing option enabled	150	200	250	mV
Δ V_OD	Change in V_OD	–	–	–	50	mV
V_OCM	Output Common Mode Voltage	RT = 100 Ω	1,125	1,250	1,375	mV
Δ V_OCM	Change in V_OCM	–	–	–	50	mV
V_OH	Output High Voltage	RT = 100 Ω	–	–	1475	mV
V_OL	Output Low Voltage	RT = 100 Ω	925	–	–	mV
I_SAB	Output Short Circuit Current	–	–	–	24	mA
LVDS RX
V_ID	Input Differential Voltage	–	100	–	600	mV
V_ICM	Input Common Mode Voltage	–	100	–	2,000	mV
V_TH	Differential Input Threshold	–	-100	–	100	mV
I_IL	Input Leakage Current	–	–	–	20	`μ`A

Table 2. LVDS Timing Specifications
Parameter	Description	Min	Typ	Max	Unit
t_{LVDS_CPA}	LVDS TX reference clock phase accuracy	-5	–	+5	%
t_{LVDS_skew}	LVDS TX lane-to-lane skew (edge-aligned)	–	–	200	ps
t_{LVDS_skew}	LVDS TX lane-to-lane skew (center-aligned)	–	–	250	ps
t_{LVDS_SU}	LVDS RX Data to CLK setup time	344	–	–	ps
t_{LVDS_HD}	LVDS RX Data to CLK hold time	344	–	–	ps