T20 Configuration Timing

The T20 FPGA has the following configuration timing specifications. Refer to AN 006: Configuring Trion FPGAs for detailed configuration information.

Table 1. Timing Parameters for All Modes (WLCSP80, Q100F3, Q144, F169, and F256 Packages)
Symbol	Parameter	Min	Typ	Max	Units
t_{CRESET_N}	Minimum creset_n low pulse width required to trigger re-configuration.	320	–	–	ns
t_USER	Minimum configuration duration after CDONE goes high before entering user mode.^¹ ^² Test condition at 10 kΩ pull-up resistance and 10 pF output loading on CDONE pin.	12	–	^³	`μ`s

Table 2. Timing Parameters for All Modes (F324 and F400 Packages)
Symbol	Parameter	Min	Typ	Max	Units
t_{CRESET_N}	Minimum creset_n low pulse width required to trigger re-configuration.	320	–	–	ns
t_USER	Minimum configuration duration after CDONE goes high before entering user mode.^¹ ^² Test condition at 10 kΩ pull-up resistance and 10 pF output loading on CDONE pin.	25	–	^³	`μ`s

¹ The FPGA may go into user mode before t_USER has elapsed. However, Efinix recommends that you keep the system interface to the FPGA in reset until t_USER has elapsed.

² For JTAG programming, the min t_USER configuration time is required after CDONE goes high and FPGA receives the ENTERUSER instruction from JTAG host (TAP controller in UPDATE_IR state).

³ See T20 Maximum tUSER for SPI Active and Passive Modes