Efinix, Inc.
  • T20 Introduction
  • T20 Features
    • T20 Available Package Options
  • T20 Device Core Functional Description
    • T20 XLR Cell
    • T20 Logic Cell
    • T20 Embedded Memory
    • T20 Multipliers
    • T20 Global Clock Network
      • T20 Clock and Control Distribution Network
      • T20 Global Clock Location (W80, Q100F3, Q144, F169, and F256)
      • T20 Global Clock Location (F324 and F400)
  • T20 Device Interface Functional Description
    • T20 Interface Block Connectivity
    • T20 General-Purpose I/O Logic and Buffer
      • T20 Complex I/O Buffer
      • T20 Double-Data I/O
    • T20 I/O Banks
    • T20 PLL
    • T20 LVDS
      • T20 LVDS TX
      • T20 LVDS RX
    • T20 MIPI
      • T20 MIPI TX
        • T20 MIPI TX Video Data TYPE[5:0] Settings
      • T20 MIPI RX
        • T20 MIPI RX Video Data TYPE[5:0] Settings
      • T20 D-PHY Timing Parameters
    • T20 DDR DRAM
      • T20 DDR Interface Designer Settings
    • T20 SPI Flash Memory
  • T20 Power Up Sequence
    • T20 Power Supply Current Transient
    • T20 Unused Resources and Features
  • T20 Configuration
    • T20 Supported Configuration Modes
    • T20 Mask-Programmable Memory Option
  • T20 DC and Switching Characteristics (W80, Q100F3, Q144, F169, and F256)
  • T20 DC and Switching Characteristics (F324 and F400)
  • T20 LVDS I/O Electrical and Timing Specifications
  • T20 ESD Performance
  • T20 MIPI Electrical Specifications and Timing
    • T20 MIPI Power-Up Timing
    • T20 MIPI Reset Timing
  • T20 PLL Timing and AC Characteristics
  • T20 Configuration Timing
    • T20 SPI Active
    • T20 SPI Passive
    • T20 JTAG
    • T20 Maximum tUSER for SPI Active and Passive Modes
  • T20 Pinout Description
    • T20 Pin States
  • T20 Efinity Software Support
  • T20 Interface Floorplans
  • T20 Ordering Codes
  • T20 Revision History

T20 ESD Performance

Refer to the Trion Reliability Report for ESD performance data.

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