Powering Embedded Computing

Sapphire RISC-V SoC

RISC-V is an open-source standard instruction set architecture (ISA) that is managed by the non-profit RISC-V Foundation. This modular ISA has a base instruction set and optional extension sets. As RISC-V is free and open-source, it has gained popularity worldwide. Over 65 RISC-V cores, both commercial and open-source, are available today.

RISC-V logo

Sapphire RISC-V SoC

Sapphire SoCEfinix has created RISC-V SoCs based on the VexRiscv core created by Charles Papon. The VexRiscv core is a 32-bit CPU using the ISA RISCV32I with M, A, F, D, and C extensions, that has six pipeline stages (fetch, injector, decode, execute, memory, and writeback), and a configurable feature set. The Sapphire SoC allows the VexRiscv core to be user configurable with the ability to support AXI4 and APB3 bus interfaces. It also comes with configurable multi-way instructions and data caches. You can easily create entire systems that include embedded compute and user-defined accelerators all in the same Titanium or Trion® FPGA

 The VexRiscv core, which won first place in the RISC-V SoftCPU contest in 2018.

The Sapphire SoC is a user-configurable, high-performance SoC with an optional memory controller. You can choose which peripherals you want by configuring the SoC in the Efinity IP Manager. This flexibility makes the Sapphire SoC ideal for a wide range of embedded applications. The Sapphire SoC is included with the Efinity IP Manager v2021.1 and higher.

  • 1 - 4 (user selectable) VexRiscv processor(s) with 6 pipeline stages (fetch, injector, decode, execute, memory, and write back), interrupts and exception handling with machine mode
  • 20 – 400 MHz system clock frequency
  • 1 - 512 KB on-chip RAM with boot loader for SPI flash
  • Memory controller for DDR3, LPDDR4x or HyperRAM memories
    • Supports memory module sizes from 4 MB to 3.5 GB
    • User-configurable external memory bus frequency
    • 1 half- duplex AXI3 interface (up to 512-bits) or 1 full-duplex AXI4 (up to 512-bits) to communicate with the external memory
    • 400 MHz DDR3 clock frequency, 800 Mbps
    • 1089 MHz LPDDR4x clock frequency, 2178 Mbps
    • 250 MHz HyperRAM clock frequency, 500 Mbps
  • Up to 2 AXI master channels for user logic, data widths from 32 to 512
  • 1 AXI slave channel to user logic
  • Includes an optional multi-way Instruction and Data Cache
  • Includes an optional Floating Point Unit (FPU)

Included with the Efinity IP Manager v2021.1 and higher

  • Includes an optional Linux Memory Management Unit (MMU)
  • Includes an optional custom instruction interface with 1,024 IDs to perform various functions
  • Supports optional RISC-V extensions such as atomic and compressed
  • APB3 peripherals:
    • Up to 32 GPIOs
    • Up to 3 I2C masters
    • Clint timer
    • Platform-Level Interrupt Controller (PLIC)
    • Up to 3 SPI masters
    • Up to 3 user timers
    • Up to 3 UARTs with 115,200 baud rate
    • Up to 5 slave user peripherals
    • Up to 8 user interrupts

Sapphire SoC Advantages

Easy to Use

Easy to Use

Configure the Sapphire SoC using the Efinity® IP Manager featuring an easy-to-use GUI.

BSP auto-generation

Board Support Package (BSP)

When user generated the customized SoC, the software creates a Board Support Package (BSP) automatically. Use the BSP to develop embedded software applications.

Design Creation

Dynamic Example Design Creation

Sapphire SoC creates example designs that following user’s SoC generation, users only require to compile and program the bitstream to start the development. The example design targeted T120F324, Ti60F225, and Ti180J484 development kits.

Sapphire SoC Block Diagram

Sapphire Multi-Core SoC Block Diagram

The Sapphire SoC incorporates up to 4 32-bit RISC-V processor that has an instruction cache with up to 8 ways and a configurable size of 1 - 32 KB, a data cache with up to 8 ways and a configurable size of 1 - 32 KB, 4 - 512 KB of on-chip RAM, and a variety of peripherals (including 1 - 5 APB3 slave peripherals and 1 AXI slave). You can configure the operating frequency from 20 - 400 MHz (the actual performance is limited by the design's fMAX). The SoC includes 1 - 3 I2C peripherals, 1 - 3 UARTs, 1 - 3 user timers, and 1 - 3 SPI masters. The SoC also features a floating-point unit (FPU), custom instruction interface, and Linux memory management unit (MMU).

The default configuration has up to a 512-bits half-duplex AXI bus to communicate with the Efinix DDR3 controller, LPDDR4x controller or HyperRAM controller.

  • DDR3 controller—This core uses the Trion FPGAs hard DDR3 DRAM interface to reset an external DRAM module (resets and re-initializes the Trion FPGA's DDR3 interface as well as the DDR3 module(s)).
  • LPDDR4x controller—This core controls LPDDR4x memory modules.
  • HyperRAM controller—This core controls HyperRAM memory modules.

You can customize the SoC using the IP Manager in the Efinity® software.

Efinity Software Support

The Sapphire SoC is fully supported by the Efinity software, which provides a complete tool flow from RTL design to bitstream generation, including synthesis, place-and-route, debugging, and timing analysis. The software has a graphical user interface (GUI) that provides a visual way to set up projects, run the tool flow, and view results. The software also has a command-line flow and Tcl command console. The software-generated bitstream file configures Trion and Titanium devices. The software supports the Verilog HDL and VHDL languages.

What's in the Package?

Efinix provides a complete package of hardware and software files. Additionally, to help you develop software applications, Efinix distributes a collection of pre-compiled open-source software.


  • SoC RTL files
  • SoC testbench
  • Example design targeting an Efinix development board


  • Board support package (BSP)
  • Linker script
  • SoC include header files
  • OpenOCD configuration files
  • Example software applications