Transmitter (TX)

The transmitter comprises a FIFO, timing flipflop, and byte serializer.

The TX FIFO compensates for clock phase differences between the transceiver (read clock) and soft logic (write clock). The PMA provides the clock source to the soft logic, which routes the clock back to the transceiver as its clock source.

The timing flipflop improves timing closure before the data is propagated to the byte serializer. TX register mode, bypassing the FIFO, is not supported currently.

The byte serializer converts the soft logic data width from 40 bits to 20 bits or 64 bits to 32 bits before feeding the 20/32-bit data to the PMA. If you do not use the byte serializer, the data width from the soft logic must be 20 or 32 bits to match the PMA data width.