Register Map

The following tables show the PMA Direct registers.

Table 1. Register Map
Register Name Type Reset Value Address[23:0] Lane/Common
std_pcs/config_reg_0 RW 0x00000000 0xC00500 Lane0
std_pcs/config_reg_1 RW 0x00000000 0xC00504
std_pcs/config_reg_2 RW 0x00000000 0xC00540 Lane1
std_pcs/config_reg_3 RW 0x00000000 0xC00544
std_pcs/config_reg_4 RW 0x00000000 0xC00580 Lane2
std_pcs/config_reg_5 RW 0x00000000 0xC00584
std_pcs/config_reg_6 RW 0x00000000 0xC005C0 Lane3
std_pcs/config_reg_7 RW 0x00000000 0xC005C4
pipe_config/config_reg_3 RW 0x00000000 0x60000C Lane0
pipe_config/config_reg_5 RW 0x00000000 0x600014 Lane1
pipe_config/config_reg_7 RW 0x00000000 0x60001C Lane2
pipe_config/config_reg_9 RW 0x00000000 0x600024 Lane3
pipe_config/config_reg_11 RW 0x00000000 0x60002C Lane0
pipe_config/config_reg_12 RW 0x00000000 0x600030 Lane1
pipe_config/config_reg_13 RW 0x00000000 0x600034 Lane2
pipe_config/config_reg_14 RW 0x00000000 0x600038 Lane3
pipe_config_cmn/config_reg_22 RW 0x00000000 0x600058 Common
Table 2. std_pcs/config_reg_0, std_pcs/config_reg_2, std_pcs/config_reg_4, std_pcs/config_reg6
Bits Name Description Type Reset
18 cfg_ser_en
To enable TX byte serializer:
1’b1: TX Core data width is two times the PHY data width
1’b0: TX Core data width is the same as the PHY data width
 RW 0
19 cfg_deser_en
To enable RX byte de-serializer:
1’b1: RX Core data width is two times the PHY data width
1’b0: RX Core data width is the same as the PHY data width
 RW 0
Table 3. std_pcs/config_reg_1, std_pcs/config_reg_3, std_pcs/config_reg_5, std_pcs/config_reg_7
Bits Name Description Type Reset
24 cfg_timing_flop_en_rx
Enable RX timing flipflop for better timing closure:
1’b1: Enable
1’b0: Disable
 RW 0
13 cfg_bypass_pcfifo_rx
Enable RX phase FIFO:
1’b1: Enable
1’b0: Disable
 RW 0
11 cfg_timing_flop_en_tx
Enable TX timing flipflop for better timing closure:
1’b1: Enable
1’b0: Disable
 RW 0
0 cfg_bypass_pcfifo_tx
Enable TX phase FIFO:
1’b1: Enable
1’b0: Disable
 RW 0
Table 4. pipe_config/config_reg_3, pipe_config/config_reg_5, pipe_config/config_reg_7, pipe_config/config_reg_9
Bits Name Description Type Reset
25:23 pma_xcvr_data_width
PHY TX and RX parallel data width:
3’b101: 20 bits
3’b010: 32 bits
RW 0
Table 5. pipe_config/config_reg_11, pipe_config/config_reg_12, pipe_config/config_reg_13, pipe_config/config_reg_14
Bits Name Description Type Reset
23 rx_polarity
RX data invert polarity.
1’b0 Polarity inversion disabled
1’b1: Polarity inversion enabled
 RW 0
22 pma_rx_termination
Receiver termination.
1’b0: Receiver high impedance.
1’b1: Receiver terminated.
Note: Assert pma_rx_termination before PMA_XCVR_PLLCLK_EN_ACK goes high in response to PMA_XCVR_PLLCLK_EN being asserted for initial startup.
 RW 0
21 pma_tx_low_power_swing_en
Transmitter low power voltage swing enable. Act as the PIPE TXSwing function. The following values are peak-to-peak (differential) values:
1’b0: 1000 mVp-p(diff)
1’b1: 400 mVp-p(diff)
 RW 0
20:18 pma_tx_vmargin
Transmitter voltage margin control. Act as the PIPE TXMargin[2:0] function.
3’b000: Maximum driver output swing
3’b110: Minimum driver output swing
3’b111: Reserved
 RW 0
17:0 pma_tx_deemphasis
Transmitter de-emphasis level control. For >2.7G data rate, the bus provides the pre-, post-, and main cursor settings as follows:
[5:0] C-1
[11:6] C0
[17:12] C+1
For ≤2.7G data rate, only bits [1:0] are used:
2’b00: 6 dB de-emphasis
2’b01: 3.5 dB de-emphasis
2’b10: No de-emphasis
2’b11: Reserved
 RW 0
Table 6. pipe_config_cmn/config_reg_22
Bits Name Description Type Reset
7:6 cfg_bonding_mode_tx3
Determines the TX bonding mode for lane 3.
00: x1
01: x2
10: x4
 RW 0
5:4 cfg_bonding_mode_tx2
Detrmines the TX bonding mode for lane 2.
00: x1
01: x2
10: x4
 RW 0
3:2 cfg_bonding_mode_tx1
Determines the TX bonding mode for lane 1.
00: x1
01: x2
10: x4
 RW 0
1:0 cfg_bonding_mode_tx0
Determines the TX bonding mode for lane 0.
00: x1
01: x2
10: x4
 RW 0