Power-Up Sequence

Initially, the PMA Direct reset controller controls the PHY_APB_PRESET_N and PHY_CMN_RESET_N signals. These PHY reset signals are handed over to the client after PMA_CMN_READY is asserted and the soft logic enters user mode. The client needs to drive both the per-lane PHY reset signals (i.e., PHY_RESET_N and PHY_CMN_RESET_N) high in the initial state so that the power up sequence, shown in the following figure, is not impacted.

When PMA_CMN_READY is asserted:

There is a 100 ns (minimum) delay between the assertion of PMA_XCVR_PLLCLK_EN_ACK and when you can set PMA_XCVR_POWER_STATE_REQ to A2.