Receiver (RX)

The receiver comprises a timing flipflop, FIFO, and byte de-serializer.

Figure 1. RX Block Diagram

The RX FIFO has the same function as the TX FIFO, it compensates for the clock phase differences between the transceiver (write clock) and soft logic (read clock).

The timing flipflop has two paths:

  • A FIFO path for better timing at the cost of extra latency.
  • A register path that has lower latency at the cost of more difficult timing closure. Refer to RX Register Mode (Design Considerations) for design guidelines.

The byte de-serializer converts the PMA data width from 20 or 32 bits to 40 or 64 bits and halves the clock frequency. If you do not use the byte de-serializer, the data width to the soft logic is 20 or 32 bits to match the PMA data width at the same clock frequency as the PMA.