Signals

In the Efinity® Interface Designer, these signal names have a user-defined prefix (e.g., <user prefix>_<signal name>). Efinix recommends that you use the following prefixes for easy quad and lane identification and traceability:
  • Lane signal prefix—Qm_Ln (e.g., Q0_L1)
  • Quad signal prefix—Qm (e.g., Q0)
Table 1. Signals per Lane
Signal Direction Clock Domain Description
TXD[63:0] Input PCS_CLK_TX Transmit data.
[19:0] and [51:32] for 20-bit and 40-bit operation.
[31:0] and [63:32] for 32-bit and 64-bit operation.
Tie unused data signals to 0.
RXD[63:0] Output PCS_CLK_RX Receive data.
[19:0] and [51:32] for 20-bit and 40-bit operation.
[31:0] and [63:32] for 32-bit and 64-bit operation.
Tie unused data signals to 0.
Clock and Reset
PCS_CLK_TX Input N/A Interface transmitter clock. Must be the same clock source as PMA_DIRECT_TX_CLK. The Efinity software connects this clock for you during PT generation.
PCS_CLK_RX Input N/A Interface receiver clock. Must be the same clock source as PMA_DIRECT_RX_CLK. The Efinity software connects this clock for you during PT generation.
PCS_RST_N_TX Input Asynchronous PCS TX reset.
PCS_RST_N_RX Input Asynchronous PCS RX reset.
PMA_DIRECT_TX_CLK Output N/A TX clock source from PMA.
PMA_DIRECT_RX_CLK Output N/A Recovered clock from PMA.
PHY_RESET_N Input Asynchronous PHY per-lane reset. The user application should initialize to 1.
Control
PMA_TX_ELEC_IDLE Input Asynchronous PMA TX electrical idle.
1’b1: TX lines placed into electrical idle state.
1’b0: Transmit data.
Power Up
PMA_XCVR_PLLCLK_EN Input Asynchronous Link PLL clock enable. This signal is used to gate the PMA_PLLCK_DATART and PMA_PLLCLK_FULLRT clocks for the associated link.
PMA_XCVR_PLLCLK_EN_ACK Output Asynchronous Link PLL clock enable acknowledgment. This signal indicates whether the PMA_PLLCLK_DATART and PMA_PLLCLK_FULLRT for the associated link is running or not.
PMA_XCVR_POWER_STATE_​REQ[3:0] Input Asynchronous Link power state request. This signal is used to change the link’s power state. When the link has completed the transition to the requested power state, the requested state is reflected on PMA_XCVR_POWER_ STATE_ACK.
4’b0000: Idle.
4’b0001: A0 - TX/RX active.
4’b0010: A1 - Powerdown1 (low power state with minimum exit latency).
4’b0100: A2 - Powerdown2 (lower power state with longer exit latency as compared to A1).
4’b1000: A3 - Powerdown3 (lower power state and longer exit latency as compared to A2).
This is a one hot encoded signal. A subsequent change request is not signaled until the current request has been acknowledged and PMA_XCVR_POWER_STATE_REQ has returned to 0.
Upon reset release, the first power state must A2.
PMA_XCVR_POWER_STATE_​ACK[3:0] Output Asynchronous Link power state acknowledgment. This signal provides indication that a power state change request has completed.
4’b000000: Value after reset, prior to first power state request
4’b0001: A0
4’b0010: A1
4’b0100: A2
4’b1000: A3
Once a power state is acknowledged, the value remains unchanged until a new power state is requested and the link has completed the transition to the new power state.
PMA_RX_SIGNAL_DETECT Output Asynchronous PMA receiver signal detect. Asserted high upon detection of a high-speed signal on the RX differential inputs.
RX Equalization Evaluation
PMA_RX_EQ_EVAL Input Asynchronous PMA receiver equalization evaluation enable.
PMA_RX_EQ_TRAINING_​DATA_VALID Input Asynchronous PMA receiver equalization training data valid. The user application should initialize to 1.
PMA_RX_EQ_EVAL_COMPLETE Output Asynchronous PMA receiver equalization complete.
PMA_RX_EQ_EVAL_STATUS Output Asynchronous PMA receiver equalization status.
PMA_RX_LINK_EVAL_FB_​DIR_CHANGE[5:0] Output Asynchronous PMA receiver equalization feedback direction change. These pins provide increment and decrement indicators for how to adjust the far end transmitter's de-emphasis setting (preemphasis, main, and post-emphasis). The increment and decrement represents the magnitude of the value. Because pre- and postemphasis are negative values, an increment would make the value more negative and a decrement would make the value less negative.
[1:0] C-1
[3:2] C0
[5:4]C+1
The value for each coefficient is as below:
00 – No change
01 – Increment
10 – Decrement
11 – Reserved
Table 2. Signals per Quad
Signal Direction Clock Domain Description
USER_APB_CLK Input N/A APB clock source, maximum 200 Mhz.
USER_APB_PADDR[23:0] Input APB_CLK

 APB address.
USER_APB_PSEL Input APB select.
USER_APB_PENABLE Input APB enable.
USER_APB_PWRITE Input APB write.
USER_APB_PWDATA[31:0] Input APB write data.
USER_APB_PRDATA[31:0] Output APB read data.
USER_APB_PREADY Output APB ready.
PMA_CMN_READY Output Asynchronous PHY ready status signal. APB interface and resets are accessible only when asserted (unless overridden in Efinity by checking the box Enable Quad Common Ready (PMA_CMN_READY) Bypass.
PHY_CMN_RESET_N Input Asynchronous PHY Quad common channel reset. The user application should initialize to 1.
Note: All the port names have a user input prefix, <user_input_prefix>_port_name. in Efinity.
Note: Efinix recommends including “Qm_Ln” (per-lane) and “Qm” (per-Quad) as the user_input_prefix for all ports for easy quad and lane identification and traceability.