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spiFlash.c
Go to the documentation of this file.
1
2// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
3// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
5
6
16#include <stdio.h>
17#include "bsp.h"
18#include "spiFlash/spiFlash.h"
19
20/* -----------------------------------------------------------------------------*/
21/* Public API: Initialization
22/* -----------------------------------------------------------------------------*/
23
25 spi_instance_t *spi = flash->inst;
26
27 // Hardware Sanity Check from user config
28 if (!IS_VALID_CPOL(spi->cpol)) spi->cpol = LOW;
29 if (!IS_VALID_CPHA(spi->cpha)) spi->cpha = DATA_SAMPLED_RISE_EDGE;
30 if (!IS_VALID_MODE(spi->mode)) spi->mode = FULL_DUPLEX_SINGLE_LINE;
31
32 if (spi->clkDivider == 0) spi->clkDivider = 2;
33 if (spi->ssSetup == 0) spi->ssSetup = 5;
34 if (spi->ssHold == 0) spi->ssHold = 2;
35 if (spi->ssDisable == 0) spi->ssDisable = 7;
36 if (spi->ssDisable == 0) spi->ssDisable = 7;
37
38 // Apply Config and wait to be completed.
39 spi_applyConfig(spi);
41}
42
43
45{
46 // Initialize SPI driver with User Config, fallback with default config if incorrect input.
48
49 // Release flash from deep power down.
50 spiFlash_wake(flash);
51
52 // Identify Flash (Type,Brand,JEDEC_ID, etc ....)
53 if (spiFlash_verify(flash, user_flash) != 0)
54 return SPI_FLASH_ERR;
55
56 // --- Load Default CMD---
57 flash-> mask_qe = 0x0;
58 flash-> cmd_exit_4byte = CMD_EXIT_4B;
59 flash-> cmd_rd_status = CMD_READ_STATUS_REG_1;
60 flash-> cmd_wr_status = CMD_WRITE_STATUS_REG_1;
61
62 // --- Checking quirk for special handling---
63 spiFlash_applyQuirks(flash);
64
65 // --- Return to 3-Byte Addressing Mode---
67
68 // If the user provided a custom setup function in the table, run it now.
69 if (flash->info->post_init_hook != NULL) {
70 flash->info->post_init_hook(flash);
71 }
72
73 return SPI_FLASH_OK;
74}
75
77 spi_instance_t *inst = flash->inst;
78 spi_select(inst,flash->cs);
79 spiFlash_wake_(flash);
80 spi_diselect(inst,flash->cs);
82 bsp_uDelay(100); // make sure the Flash fully awake
83}
84
85
86/* -----------------------------------------------------------------------------*/
87/* Internal API: Initialization
88/* -----------------------------------------------------------------------------*/
89
90static void spiFlash_applyQuirks(spiFlash_instance_t *flash)
91{
92 u32 flags = flash->info->flags;
93
94 // --- Quirk: Write Protection ---
95 if (flags & FLAG_UNLOCK_ON_PROBE) {
96 u8 status = spiFlash_readStatusReg(flash);
97 if (status & 0xBC) { // Check if any protection bits (BP0-3, SRWD) are actually set
99 spiFlash_writeStatusReg(flash, status & 0x43);
100 LOG_INFO(DBG_MOD_RTC,"OK: Protection bits cleared.");
101 }
102 }
103
104 // --- Quirk: 4-Byte Exit Command ---
105 if (flags & FLAG_4BYTE_EXIT_ISSI) {
106 flash->cmd_exit_4byte = CMD_EXIT_4B_ISSI; // ISSI ONLY
107 } else {
108 flash->cmd_exit_4byte = CMD_EXIT_4B; // Default
109 }
110
111 // --- Quirk: Quad Enable Configuration ---
112 if (flags & FLAG_QE_SR2_BIT1) { //Windbond ONLY
113 flash->mask_qe = QE_BIT1;
116 }
117 else if (flags & FLAG_QE_SR1_BIT6) { //Macronix & ISSI
118 flash->mask_qe = QE_BIT6;
120 }
121
122}
123
124static void spiFlash_wake_(spiFlash_instance_t *flash)
125{
126 spi_instance_t *inst = flash->inst;
128}
129
130
131
132/* -----------------------------------------------------------------------------*/
133/* SPI FLASH Identify Operation - Public API
134/* -----------------------------------------------------------------------------*/
135
137{
138 // Check JEDEC ID and store it in detected_id variable.
139 flash->detected_id = spiFlash_jedec_id(flash);
140
141 // Hardware Sanity Check
142 if (flash->detected_id == 0x000000 || flash->detected_id == 0xFFFFFF) {
143 LOG_ERR(DBG_MOD_SPI_FLASH,"SPI Bus Failure! ID: 0x%06X", flash->detected_id);
144 return SPI_FLASH_ERR;
145 }
146
147 // Initialize to safe state
148 flash->info = NULL;
149 const spiFlash_info_t* tables[] = { user_flash, known_flash };
150 // Identify Flash
151 for (int i = 0; i < 2; i++) {
152 if (tables[i] != NULL) {
153 flash->info = identifyFlash(flash->detected_id, tables[i]);
154 if (flash->info == NULL && i ==0) LOG_WARN(DBG_MOD_SPI_FLASH,
155 "User flash is not found/match, checking with known flash."); // userflash not exist.
156 if (flash->info != NULL) break; // Found a match!
157 }
158 }
159
160 if (flash->info == NULL) {
161 LOG_ERR(DBG_MOD_SPI_FLASH, "Unknown Flash (ID: 0x%06X). Please register ID.", flash->detected_id);
162 return SPI_FLASH_ERR;
163 }
164
165 LOG_INFO(DBG_MOD_SPI_FLASH, "%s Flash is found!",flash->info->part_no);
166 LOG_INFO(DBG_MOD_SPI_FLASH, "Detected JEDEC_ID: 0x%X.",flash->detected_id);
167
168 return SPI_FLASH_OK;
169}
170
171
173{
174 spi_instance_t *inst = flash->inst;
175 spi_select(inst,flash->cs);
176 u8 data = spiFlash_read_id_(flash);
177 spi_diselect(inst,flash->cs);
178 return data;
179}
180
182{
183 spi_instance_t *inst = flash->inst;
184 spi_select(inst,flash->cs);
185 flash->detected_id = spiFlash_jedec_id_(flash);
186 spi_select(inst,flash->cs);
187 return flash->detected_id;
188}
189
190
191/* -----------------------------------------------------------------------------*/
192/* Internal API: Identify Operation
193/* -----------------------------------------------------------------------------*/
194
195static const spiFlash_info_t * identifyFlash(u32 detected_id, const spiFlash_info_t *table)
196{
197 if (table == NULL) return NULL; // If NULL, expect to use generic flash. (UserFlash not exist)
198
199 for (int i = 0; table[i].part_no != NULL; i++) {
200 if (table[i].jedec_id == detected_id) {
201 return &table[i];
202 }
203 }
204 return NULL; //Return user table (UserFlash not match)
205}
206
207
208static u8 spiFlash_read_id_(spiFlash_instance_t *flash){
209 spi_instance_t *inst = flash->inst;
211 spi_write(inst, 0x00); // Dummy Data
212 spi_write(inst, 0x00); // Dummy Data
213 spi_write(inst, 0x00); // Dummy Data
214 return spi_read(inst);
215}
216
217static u32 spiFlash_jedec_id_(spiFlash_instance_t *flash) {
218 spi_instance_t *inst = flash->inst;
219 u32 id = 0;
221 // Ensure the command is sent before reading
222 spi_waitUntilIdle(inst);
223 // Read 3 bytes and pack them into a 24-bit integer
224 id |= (u32)spi_read(inst) << 24; // Manufacturer ID
225 id |= (u32)spi_read(inst) << 16; // Memory Type
226 id |= (u32)spi_read(inst) << 8; // Capacity Code
227 return id;
228}
229
230
231/* -----------------------------------------------------------------------------*/
232/* Public API: Read/Write Operation
233/* -----------------------------------------------------------------------------*/
234
235// Use to write 256 byte only!
236u8 spiFlash_write(spiFlash_instance_t *flash, u32 flashAddress, u8 *src, u32 len)
237{
238 spi_instance_t *inst = flash-> inst;
240 spiFlash_sectorErase(flash,flashAddress);
242 spi_select(inst,flash->cs);
244 spi_write(inst, (flashAddress>>16) & 0xFF);
245 spi_write(inst, (flashAddress>>8) & 0xFF);
246 spi_write(inst, (flashAddress>>0) & 0xFF);
247 for(int i=0; i<len; i++)
248 {
249 spi_write(inst, src[i] );
250 }
251 spi_diselect(inst,flash->cs);
252 if (spiFlash_waitBusy(flash) == 1) return SPI_FLASH_ERR;
253 spiFlash_globalLock(flash);
254 return SPI_FLASH_OK;
255}
256
257
258u8 spiFlash_write_quad(spiFlash_instance_t *flash, u32 flashAddress, u8 *src, u32 len)
259{
260 spi_instance_t *inst = flash-> inst;
262 spiFlash_sectorErase(flash,flashAddress);
264 spi_select(inst,flash->cs);
266 spi_write(inst, (flashAddress>>16) & 0xFF);
267 spi_write(inst, (flashAddress>>8) & 0xFF);
268 spi_write(inst, (flashAddress>>0) & 0xFF);
269 for(int i=0; i<len; i++)
270 {
271 spi_write(inst, src[i] );
272 }
273 spi_diselect(inst,flash->cs);
274 if (spiFlash_waitBusy(flash) == 1) return SPI_FLASH_ERR;
275 spiFlash_globalLock(flash);
276 return SPI_FLASH_OK;
277}
278
279void spiFlash_read(spiFlash_instance_t *flash, u32 flashAddress, u8 *buffer, u32 len)
280{
281 spi_instance_t *inst = flash->inst;
282 spi_select(inst,flash->cs);
284 spi_write(inst, (flashAddress>>16) & 0xFF);
285 spi_write(inst, (flashAddress>>8) & 0xFF);
286 spi_write(inst, (flashAddress>>0) & 0xFF);
287 for (u32 i = 0; i < len; i++)
288 {
289 buffer[i] = spi_read(inst);
290 }
291 spi_diselect(inst,flash->cs);
292}
293
294void spiFlash_read_quad(spiFlash_instance_t *flash, u32 flashAddress, u8 *buffer, u32 len)
295{
296 spi_instance_t *inst = flash->inst;
297 spi_select(inst,flash->cs);
299 spi_write(inst, (flashAddress >> 16) & 0xFF);
300 spi_write(inst, (flashAddress >> 8) & 0xFF);
301 spi_write(inst, (flashAddress >> 0) & 0xFF);
302 spi_write(inst, 0x00);
303 spi_write(inst, 0);
304 spi_write(inst, 0);
305 for (u32 i = 0; i < len; i++)
306 {
307 buffer[i] = spi_read(inst);
308 }
309 spi_diselect(inst,flash->cs);
310}
311
312/*******************************************************************************
313*
314* @brief This function read Status Register.
315*
316* @param reg SPI base address
317* @param cs 32-bit bitwise chip select setting
318*
319******************************************************************************/
321{
322 spi_instance_t *inst = flash->inst;
323 spi_select(inst,flash->cs);
324 spi_write(inst, flash->cmd_rd_status); //Read Status Register
325 u8 value = spi_read(inst);
326 spi_diselect(inst,flash->cs);
327 return value;
328}
329
330/*******************************************************************************
331*
332* @brief This function write Status Register.
333*
334* @param reg SPI base address
335* @param cs 32-bit bitwise chip select setting
336* @param data 8-bit data
337*
338******************************************************************************/
340{
341 spi_instance_t *inst = flash->inst;
342 spi_select(inst,flash->cs);
343 spi_write(inst, flash->cmd_wr_status); //Write Status Register
344 spi_write(inst, data); //Write Status Register
345 spi_diselect(inst,flash->cs);
346}
347
348
349void spiFlash_f2m(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
350{
351 spi_select(flash->inst,flash->cs);
352 spiFlash_f2m_(flash, flashAddress, memoryAddress, size);
353 spi_diselect(flash->inst,flash->cs);
354}
355
356void spiFlash_f2m_dual(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
357{
358 spi_select(flash->inst,flash->cs);
359 spiFlash_dual_f2m_(flash, flashAddress, memoryAddress, size);
360 spi_diselect(flash->inst,flash->cs);
361}
362
363void spiFlash_f2m_quad(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
364{
365 spi_select(flash->inst,flash->cs);
366 spiFlash_quad_f2m_(flash, flashAddress, memoryAddress, size);
367 spi_diselect(flash->inst,flash->cs);
368}
369
370
371/* -----------------------------------------------------------------------------*/
372/* Public API: Enablement Operation
373/* -----------------------------------------------------------------------------*/
374
376{
377 u8 status = 0;
378 spi_instance_t *inst = flash->inst;
379
380 // Set Write Enable Latch (WEL) by sending CMD-0x06
381 do {
382 spiFlash_writeEnable(flash);
383 status = spiFlash_readStatusReg(flash);
384 bsp_uDelay(1);
385 } while ((status & WEL_BIT) != WEL_BIT); // 0x02 is standard WEL bit
386
387 // 1. Mask the existing Status Register Bit-Flip (Winbond/Macronix)
388 if (flash->info->flags & FLAG_QE_ENABLE_VIA_SR) {
389 spiFlash_writeStatusReg(flash, status | flash->mask_qe);
390 do {
391 status = spiFlash_readStatusReg(flash);
392 bsp_uDelay(1);
393 } while ((status & flash->mask_qe) != flash->mask_qe);
394 }
395
396 // 2. Direct write to register (GigaDevice)
397 else if (flash->info->flags & FLAG_QE_CMD_38) {
398 spi_select(inst,flash->cs);
400 spi_diselect(inst,flash->cs);
401 }
402}
403
404
406{
407 spi_instance_t *inst = flash->inst;
408 spi_select(inst,flash->cs);
409 spi_write(inst, CMD_WRITE_ENABLE); // Write Enable Sequence
410 spi_diselect(inst,flash->cs);
411}
412
414{
415 spi_instance_t *inst = flash->inst;
416
417 if (flash->info->flags & FLAG_4BYTE_SUPPORT)
418 {
419 spi_waitUntilIdle(inst);
420 spi_select(inst,flash->cs);
421 spi_write(inst,flash->cmd_exit_4byte);
422 spi_diselect(inst,flash->cs);
423 spi_waitUntilIdle(inst);
424
425 return SPI_FLASH_OK;
426 }
427 else return SPI_FLASH_SKIP;
428
429}
430
432{
433 spi_instance_t *inst = flash->inst;
435 spi_select(inst,flash->cs);
437 spi_diselect(inst,flash->cs);
438}
439
441{
442 spi_instance_t *inst = flash->inst;
444 spi_select(inst,flash->cs);
446 spi_diselect(inst,flash->cs);
447}
448
450{
451 u8 out;
452 u16 timeout=0;
453 while(1)
454 {
455 bsp_uDelay(1*1000);
456 out = spiFlash_readStatusReg(flash);
457 if((out & 0x01) ==0x00)
458 return SPI_FLASH_OK;
459 timeout++;
460 //sector erase max=400ms
461 if(timeout >=400)
462 {
463 return SPI_FLASH_ERR; //Time out
464 }
465 }
466}
467
469{
470 spi_instance_t *inst = flash->inst;
472 spi_select(inst,flash->cs);
474 spi_write(inst, (flashAddress>>16)&0xFF);
475 spi_write(inst, (flashAddress>>8)&0xFF);
476 spi_write(inst, (flashAddress>>0)&0xFF);
477 spi_diselect(inst,flash->cs);
478 spiFlash_waitBusy(flash);
479}
480
481/* -----------------------------------------------------------------------------*/
482/* Internal: Read/Write Operation
483/* -----------------------------------------------------------------------------*/
484
485static void spiFlash_f2m_(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size){
486 spi_instance_t *inst = flash->inst;
488 spi_write(inst, flashAddress >> 16);
489 spi_write(inst, flashAddress >> 8);
490 spi_write(inst, flashAddress >> 0);
491 spi_write(inst, 0);
492 u8 *ram = (u8 *) memoryAddress;
493 for(u32 idx = 0;idx < size;idx++){
494 *ram++ = spi_read(inst);
495 }
496
497}
498
499static void spiFlash_dual_f2m_(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size){
500 spi_instance_t *inst = flash->inst;
502 spi_write(inst, flashAddress >> 16);
503 spi_write(inst, flashAddress >> 8);
504 spi_write(inst, flashAddress >> 0);
505 spi_write(inst, 0);
506 spi_waitUntilIdle(inst);
508 u8 *ram = (u8 *) memoryAddress;
509 for(u32 idx = 0;idx < size;idx++){
510 *ram++ = spi_read(inst);
511 }
512 spi_setDataMode(inst,FULL_DUPLEX_SINGLE_LINE);// change mode back to single data mode
513}
514
515//TODO: Need to test for gigabit device!!
516static void spiFlash_quad_f2m_(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size){
517 spi_instance_t *inst = flash->inst;
519 spi_write(inst, flashAddress >> 16);
520 spi_write(inst, flashAddress >> 8);
521 spi_write(inst, flashAddress >> 0);
522 spi_write(inst, 0);
523 spi_waitUntilIdle(inst);
524 spi_setDataMode(inst, HALF_DUPLEX_QUAD_LINE); // change mode to quad data mode
525 uint8_t *ram = (uint8_t *) memoryAddress;
526 for(u32 idx = 0;idx < size;idx++){
527 *ram++ = spi_read(inst);
528 }
529 spi_setDataMode(inst, FULL_DUPLEX_SINGLE_LINE); // change mode back to single data mode
530}
531
#define bsp_uDelay(usec)
Definition bsp.h:31
#define LOG_WARN(debug, fmt,...)
Definition debug.h:238
#define LOG_INFO(debug, fmt,...)
Definition debug.h:237
#define LOG_ERR(debug, fmt,...)
Definition debug.h:239
#define DBG_MOD_SPI_FLASH
SPI Flash Driver.
Definition debug.h:108
#define DBG_MOD_RTC
Real Time Clock.
Definition debug.h:109
const spiFlash_info_t known_flash[]
Supported Flash Info.
@ FULL_DUPLEX_SINGLE_LINE
Full-duplex mode using single data lin.
Definition spi.h:118
@ HALF_DUPLEX_QUAD_LINE
Half-duplex mode using quad data lin.
Definition spi.h:120
@ HALF_DUPLEX_DUAL_LINE
Half-duplex mode using dual data lin.
Definition spi.h:119
@ LOW
Clock is low when id.
Definition spi.h:125
@ DATA_SAMPLED_RISE_EDGE
Data sampled on rising clock ed.
Definition spi.h:131
#define FLAG_QE_ENABLE_VIA_SR
Check if QE requires a Status Register Write.
#define FLAG_QE_SR1_BIT6
Method B: Macronix/ISSI Style (Status Register 1).
#define FLAG_QE_SR2_BIT1
Method A: Winbond Style (Status Register 2).
#define FLAG_4BYTE_EXIT_ISSI
Quirk: ISSI-Specific 4-Byte Exit.
#define FLAG_UNLOCK_ON_PROBE
Quirk: Auto-Lock on Power Up.
#define FLAG_4BYTE_SUPPORT
Supports 4-Byte Addressing Mode.
#define FLAG_QE_CMD_38
Method C: GigaDevice Command.
spiFlash_status_t
SPI Flash transfer mode configuration.
Definition spiFlash.h:153
@ SPI_FLASH_OK
Successful Operation *‍/.
Definition spiFlash.h:154
@ SPI_FLASH_ERR
Unknown JEDEC ID, Electrical failure (0x00/0xFF) *‍/.
Definition spiFlash.h:155
@ SPI_FLASH_SKIP
Skip the function *‍/.
Definition spiFlash.h:156
void spiFlash_writeStatusReg(spiFlash_instance_t *flash, u8 data)
Write Status Register.
Definition spiFlash.c:339
void spiFlash_read_quad(spiFlash_instance_t *flash, u32 flashAddress, u8 *buffer, u32 len)
Read N byte from Flash using quad read mode.
Definition spiFlash.c:294
void spiFlash_writeEnable(spiFlash_instance_t *flash)
Set Write Enable Latch.
Definition spiFlash.c:405
spiFlash_status_t spiFlash_verify(spiFlash_instance_t *flash, const spiFlash_info_t *user_flash)
Verify spiFlash.
Definition spiFlash.c:136
void spiFlash_sectorErase(spiFlash_instance_t *flash, u32 flashAddress)
Erases a sector of the SPI flash given an address.
Definition spiFlash.c:468
u32 spiFlash_jedec_id(spiFlash_instance_t *flash)
Select and read JEDEC ID from spiFlash.
Definition spiFlash.c:181
u8 spiFlash_read_id(spiFlash_instance_t *flash)
Select and Read Device ID from spiFlash.
Definition spiFlash.c:172
void spiFlash_read(spiFlash_instance_t *flash, u32 flashAddress, u8 *buffer, u32 len)
Read N byte from Flash using standard read mode.
Definition spiFlash.c:279
void spiFlash_enable_quad_access(spiFlash_instance_t *flash)
Set Write Enable Latch and set Quad Enable bit to enable Quad SPI.
Definition spiFlash.c:375
spiFlash_status_t spiFlash_waitBusy(spiFlash_instance_t *flash)
Wait for spiFlash to be free.
Definition spiFlash.c:449
u8 spiFlash_write_quad(spiFlash_instance_t *flash, u32 flashAddress, u8 *src, u32 len)
Write N byte to Flash using quad write mode.
Definition spiFlash.c:258
u8 spiFlash_readStatusReg(spiFlash_instance_t *flash)
Read Status Register.
Definition spiFlash.c:320
void spiFlash_globalUnlock(spiFlash_instance_t *flash)
Globally unlocks the SPI flash.
Definition spiFlash.c:440
u8 spiFlash_write(spiFlash_instance_t *flash, u32 flashAddress, u8 *src, u32 len)
Write N byte to Flash using standard write mode.
Definition spiFlash.c:236
u8 spiFlash_exit4ByteAddr(spiFlash_instance_t *flash)
Exit 4-byte addressing.
Definition spiFlash.c:413
void spiFlash_f2m(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
This function read data from FlashAddress and copy to memoryAddress of specific size with single data...
Definition spiFlash.c:349
void spiFlash_init_controller(spiFlash_instance_t *flash)
Initialize SPI setting.
Definition spiFlash.c:24
void spiFlash_globalLock(spiFlash_instance_t *flash)
Globally locks the SPI flash.
Definition spiFlash.c:431
spiFlash_status_t spiFlash_probe(spiFlash_instance_t *flash, const spiFlash_info_t *user_flash)
The main wrapper for initialize SPI Flash.
Definition spiFlash.c:44
void spiFlash_wake(spiFlash_instance_t *flash)
Select spi and wake up SPI Flash.
Definition spiFlash.c:76
#define QE_BIT1
This Macro specifically for Windbond Flash to enable Quad Mode **‍/.
Definition spiFlash.h:129
#define CMD_PAGE_PROGRAM
Standard Write Page (256 Bytes) **‍/.
Definition spiFlash.h:76
#define CMD_READ_STATUS_REG_1
Standard Read Status Register 1 (WIP, WEL, BP) **‍/.
Definition spiFlash.h:63
#define CMD_SECTOR_ERASE
Standard Erase 4KB Sector **‍/.
Definition spiFlash.h:119
#define CMD_GLOBAL_UNLOCK
Standard Global Block Unlock **‍/.
Definition spiFlash.h:102
#define CMD_ENABLE_QUAD_GD
To enable Quad Mode, need to write to this register for (*GigaDevice Quirk) **‍/.
Definition spiFlash.h:103
#define QE_BIT6
This Macro specifically for Macronix & ISIS Flash to enable Quad Mode **‍/.
Definition spiFlash.h:128
#define CMD_QUAD_PAGE_PROGRAM
Standard Write Page (256 Bytes) **‍/.
Definition spiFlash.h:77
#define CMD_WRITE_STATUS_REG_1
Standard Write SR1 (Macronix/ISSI/Standard) **‍/.
Definition spiFlash.h:66
#define CMD_GLOBAL_LOCK
Standard Global Block Lock **‍/.
Definition spiFlash.h:101
#define CMD_READ_DATA
Standard Read (up to 33MHz) **‍/.
Definition spiFlash.h:87
#define CMD_FAST_READ
Standard Read at higher speed **‍/.
Definition spiFlash.h:88
#define CMD_READ_DEVICE_ID
Standard Read device ID (legacy) **‍/.
Definition spiFlash.h:55
#define CMD_READ_STATUS_REG_2
Read Status Register 2 (*QE for Winbond) **‍/.
Definition spiFlash.h:64
#define CMD_EXIT_4B_ISSI
Exit 4-Byte Mode (*ISSI Quirk) **‍/.
Definition spiFlash.h:114
#define CMD_WRITE_ENABLE
Standard Set WEL Bit **‍/.
Definition spiFlash.h:78
#define CMD_DUAL_OUTPUT_READ
Standard Double throughput in read mode.**‍/.
Definition spiFlash.h:89
#define CMD_QUAD_OUTPUT_READ
Standard Quad throughput in read mode.**‍/.
Definition spiFlash.h:90
#define CMD_EXIT_4B
Standard Exit 4-Byte Mode (Standard) **‍/.
Definition spiFlash.h:113
#define CMD_WRITE_STATUS_REG_2
Write SR2 (*Winbond Specific Quirk) **‍/.
Definition spiFlash.h:67
#define CMD_READ_JEDEC_ID
Standard Read JEDEC ID (Manuf + Type + Cap) **‍/.
Definition spiFlash.h:54
#define CMD_RELEASE_DEEP_POWER_DOWN
Standard Release flash from deep power down. *‍/.
Definition spiFlash.h:98
#define WEL_BIT
Write Enable Latch Bit in Status Reg **‍/.
Definition spiFlash.h:130
u8 spi_read(spi_instance_t *inst)
Reads an 8-bit data value from the SPI read register.
Definition spi.c:71
void spi_waitUntilIdle(spi_instance_t *inst)
Waits for SPI if it has any command waiting to be executed in queue.
Definition spi.c:150
void spi_diselect(spi_instance_t *inst, u32 cs)
Deselects the SPI slave by deasserting the corresponding chip select (CS) line.
Definition spi.c:132
void spi_applyConfig(spi_instance_t *inst)
Applies the current configuration settings stored in the spi_instance_t structure to the SPI hardware...
Definition spi.c:93
void spi_write(spi_instance_t *inst, u8 data)
Writes an 8-bit data value to the SPI data register.
Definition spi.c:105
void spi_setDataMode(spi_instance_t *inst, enum cfg_mode Mode)
Set SPI Data Mode (Full/Half Duplex, Dual/Quad Line).
Definition spi.c:25
void spi_select(spi_instance_t *inst, u32 cs)
Selects the SPI slave by asserting the corresponding chip select (CS) line.
Definition spi.c:123
void spiFlash_f2m_dual(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
Definition spiFlash.c:356
void spiFlash_f2m_quad(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
Definition spiFlash.c:363
SPI Flash driver API definitions.
SPI instance. Holds the software registers and hardware pointer.
Definition spi.h:212
enum cfg_mode mode
Stored Transfer Mode.
Definition spi.h:216
u32 ssSetup
Slave Select Setup Cycles.
Definition spi.h:218
u32 clkDivider
Clock Divider Value.
Definition spi.h:217
enum cfg_cpol cpol
Stored Clock Polarity.
Definition spi.h:214
enum cfg_cpha cpha
Stored Clock Phase.
Definition spi.h:215
u32 ssHold
Slave Select Hold Cycles.
Definition spi.h:219
u32 ssDisable
Slave Select Disable Cycles.
Definition spi.h:220
SPI Flash Device Descriptor.
const char * part_no
flash_hook post_init_hook
SPI Flash instance structure.
Definition spiFlash.h:184
u8 cs
Chip select *‍/.
Definition spiFlash.h:188
u32 detected_id
JEDEC_ID = Manu_id, mem_type, capacity *‍/.
Definition spiFlash.h:187
u8 cmd_exit_4byte
CMD for exit 4 byte addressing *‍/.
Definition spiFlash.h:193
u8 mask_qe
CMD for Quad Enable Bit *‍/.
Definition spiFlash.h:194
u8 cmd_wr_status
CMD for Write Status *‍/.
Definition spiFlash.h:192
const spiFlash_info_t * info
Flash Descriptor *‍/.
Definition spiFlash.h:186
u8 cmd_rd_status
CMD for Read Status *‍/.
Definition spiFlash.h:191
spi_instance_t * inst
Pointer to shared SPI Master *‍/.
Definition spiFlash.h:185
uint8_t u8
Definition type.h:26
uint16_t u16
Definition type.h:24
uint32_t u32
Definition type.h:22