RV32 SoC DS UG
High-Perf RV32 SoC DS UG
RV64 SoC DS UG API and Examples
Embedded IDE UG
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spiFlash.c
Go to the documentation of this file.
1
2// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
3// Full license header bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
5
6
16#include <stdio.h>
17#include "bsp.h"
18#include "spiFlash/spiFlash.h"
19
20/* -----------------------------------------------------------------------------*/
21/* Public API: Initialization
22/* -----------------------------------------------------------------------------*/
23
24static const spiFlash_info_t *user_flash_table = NULL;
25static size_t user_flash_count = 0;
26
27void spiFlash_registerFlash(const spiFlash_info_t *table, size_t count)
28{
29 user_flash_table = table;
30 user_flash_count = count;
31}
32
34 spi_instance_t *spi = flash->inst;
35
36 // Hardware Sanity Check from user config
37 if (!IS_VALID_CPOL(spi->cpol)) {
38 spi->cpol = LOW;
39 LOG_WARN(DBG_MOD_SPI_FLASH,"SPI CPOL is not valid, applying default config.");
40 }
41 if (!IS_VALID_CPHA(spi->cpha)) {
43 LOG_WARN(DBG_MOD_SPI_FLASH,"SPI CPHA is not valid, applying default config.");
44 }
45 if (!IS_VALID_MODE(spi->mode)) {
47 LOG_WARN(DBG_MOD_SPI_FLASH,"SPI MODE is not valid, applying default config.");
48 }
49
50 if (spi->clkDivider == 0) spi->clkDivider = 2;
51 if (spi->ssSetup == 0) spi->ssSetup = 5;
52 if (spi->ssHold == 0) spi->ssHold = 2;
53 if (spi->ssDisable == 0) spi->ssDisable = 7;
54 if (spi->clkDivider == 0 || spi->ssSetup == 0 || spi->ssHold == 0 || spi->ssDisable == 0) {
55 LOG_WARN(DBG_MOD_SPI_FLASH,"SPI timing parameters are not valid, applying default config.");
56 }
57 // Apply Config and wait to be completed.
59}
60
61
63{
64 // Initialize SPI driver with User Config, fallback with default config if incorrect input.
66
67 // Release flash from deep power down.
68 spiFlash_wake(flash);
69
70 // Identify Flash (Type,Brand,JEDEC_ID, etc ....)
71 if (spiFlash_verify(flash) != 0)
72 return SPI_FLASH_ERR;
73
74 // --- Load Default CMD---
75 flash-> mask_qe = 0x0;
76 flash-> cmd_exit_4byte = CMD_EXIT_4B;
77 flash-> cmd_rd_status = CMD_READ_STATUS_REG_1;
78 flash-> cmd_wr_status = CMD_WRITE_STATUS_REG_1;
79
80 // --- Checking quirk for special handling---
82
83 // --- Return to 3-Byte Addressing Mode---
85
86 // If the user provided a custom setup function in the table, run it now.
87 if (flash->info->post_init_hook != NULL) {
88 flash->info->post_init_hook(flash);
89 }
90
91 return SPI_FLASH_OK;
92}
93
99
101 spi_instance_t *inst = flash->inst;
102 spi_select(inst,flash->cs);
103 spiFlash_wake_(flash);
104 spi_deselect(inst,flash->cs);
105 spi_waitUntilIdle(inst);
106 bsp_uDelay(100); // make sure the Flash fully awake
107}
108
109/* -----------------------------------------------------------------------------*/
110/* Internal API: Initialization
111/* -----------------------------------------------------------------------------*/
112
113static void spiFlash_wake_(spiFlash_instance_t *flash)
114{
115 spi_instance_t *inst = flash->inst;
117}
118
119
120
121/* -----------------------------------------------------------------------------*/
122/* SPI FLASH Identify Operation - Public API
123/* -----------------------------------------------------------------------------*/
124
126{
127 spi_instance_t *inst = flash->inst;
128 spi_select(inst,flash->cs);
129 u8 data = spiFlash_readId_(flash);
130 spi_deselect(inst,flash->cs);
131 return data;
132}
133
135{
136 spi_instance_t *inst = flash->inst;
137 spi_select(inst,flash->cs);
138 flash->detected_id = spiFlash_readJedecId_(flash);
139 spi_deselect(inst,flash->cs);
140 return flash->detected_id;
141}
142
144{
145 // User table first — allows override of built-in entries
146 if (user_flash_table != NULL) {
147 for (size_t i = 0; i < user_flash_count; i++) {
148 if (user_flash_table[i].jedec_id == detected_id)
149 return &user_flash_table[i]; // found → stop immediately
150 }
151 LOG_WARN(DBG_MOD_SPI_FLASH,"User flash is not found/match, checking with known flash.");
152 }
153
154 // Fallback to built-in
155 for (size_t i = 0; known_flash[i].part_no != NULL; i++) {
156 if (known_flash[i].jedec_id == detected_id)
157 LOG_INFO(DBG_MOD_SPI_FLASH,"Flash is detected from known table.");
158 return &known_flash[i];
159 }
160
161 return NULL;
162}
163
165{
166 // Check JEDEC ID and store it in detected_id variable.
167 flash->detected_id = spiFlash_readJedecId(flash);
168
169 // Hardware Sanity Check
170 if (flash->detected_id == 0x000000 || flash->detected_id == 0xFFFFFF) {
171 LOG_ERR(DBG_MOD_SPI_FLASH,"SPI Bus Failure! ID: 0x%06X", flash->detected_id);
172 return SPI_FLASH_ERR;
173 }
174
175 // Identify Flash with user table first, then fallback to built-in table.
176 flash->info = spiFlash_lookup(flash->detected_id);
177 if (flash->info == NULL) {
178 LOG_ERR(DBG_MOD_SPI_FLASH, "Unknown Flash (ID: 0x%06X). Please register ID.", flash->detected_id);
179 return SPI_FLASH_ERR;
180 }
181
182 LOG_INFO(DBG_MOD_SPI_FLASH, "%s Flash is found!",flash->info->part_no);
183 LOG_INFO(DBG_MOD_SPI_FLASH, "Detected JEDEC_ID: 0x%X.",flash->detected_id);
184
185 return SPI_FLASH_OK;
186}
187
188
190{
191 u32 flags = flash->info->flags;
192
193 // --- Quirk: Write Protection ---
194 if (flags & FLAG_UNLOCK_ON_PROBE) {
195 u8 status = spiFlash_readStatusReg(flash);
196 if (status & 0xBC) { // Check if any protection bits (BP0-3, SRWD) are actually set
198 spiFlash_writeStatusReg(flash, status & 0x43);
199 LOG_INFO(DBG_MOD_RTC,"OK: Protection bits cleared.");
200 }
201 }
202
203 // --- Quirk: 4-Byte Exit Command ---
204 if (flags & FLAG_4BYTE_EXIT_ISSI) {
205 flash->cmd_exit_4byte = CMD_EXIT_4B_ISSI; // ISSI ONLY
206 } else {
207 flash->cmd_exit_4byte = CMD_EXIT_4B; // Default
208 }
209
210 // --- Quirk: Quad Enable Configuration ---
211 if (flags & FLAG_QE_SR1_BIT6) { //Macronix & ISSI
212 flash->mask_qe = QE_BIT6;
214 }
215
216}
217
218/* -----------------------------------------------------------------------------*/
219/* Internal API: Identify Operation
220/* -----------------------------------------------------------------------------*/
221
222static u8 spiFlash_readId_(spiFlash_instance_t *flash){
223 spi_instance_t *inst = flash->inst;
225 spi_write(inst, 0x00); // Dummy Data
226 spi_write(inst, 0x00); // Dummy Data
227 spi_write(inst, 0x00); // Dummy Data
228 return spi_read(inst);
229}
230
231static u32 spiFlash_readJedecId_(spiFlash_instance_t *flash) {
232 spi_instance_t *inst = flash->inst;
233 u32 id = 0;
235 // Ensure the command is sent before reading
236 spi_waitUntilIdle(inst);
237 // Read 3 bytes and pack them into a 24-bit integer
238 id |= (u32)spi_read(inst) << 24; // Manufacturer ID
239 id |= (u32)spi_read(inst) << 16; // Memory Type
240 id |= (u32)spi_read(inst) << 8; // Capacity Code
241 return id;
242}
243
244
245/* -----------------------------------------------------------------------------*/
246/* Public API: Read/Write Operation
247/* -----------------------------------------------------------------------------*/
248
249u8 spiFlash_write_single(spiFlash_instance_t *flash, u32 flashAddress, u8 *src, u32 len)
250{
251 spi_instance_t *inst = flash-> inst;
253 spiFlash_eraseSector(flash,flashAddress);
255 spi_select(inst,flash->cs);
257 spi_write(inst, (flashAddress>>16) & 0xFF);
258 spi_write(inst, (flashAddress>>8) & 0xFF);
259 spi_write(inst, (flashAddress>>0) & 0xFF);
260 for(int i=0; i<len; i++)
261 {
262 spi_write(inst, src[i] );
263 }
264 spi_deselect(inst,flash->cs);
265 if (spiFlash_waitBusy(flash) == 1) return SPI_FLASH_ERR;
266 spiFlash_lockGlobal(flash);
267 return SPI_FLASH_OK;
268}
269
270void spiFlash_read_single(spiFlash_instance_t *flash, u32 flashAddress, u8 *buffer, u32 len)
271{
272 spi_instance_t *inst = flash->inst;
273 spi_select(inst,flash->cs);
275 spi_write(inst, (flashAddress>>16) & 0xFF);
276 spi_write(inst, (flashAddress>>8) & 0xFF);
277 spi_write(inst, (flashAddress>>0) & 0xFF);
278 for (u32 i = 0; i < len; i++)
279 {
280 buffer[i] = spi_read(inst);
281 }
282 spi_deselect(inst,flash->cs);
283}
284
285
286/*******************************************************************************
287*
288* @brief This function read Status Register.
289*
290* @param reg SPI base address
291* @param cs 32-bit bitwise chip select setting
292*
293******************************************************************************/
295{
296 spi_instance_t *inst = flash->inst;
297 spi_select(inst,flash->cs);
298 spi_write(inst, flash->cmd_rd_status); //Read Status Register
299 u8 value = spi_read(inst);
300 spi_deselect(inst,flash->cs);
301 return value;
302}
303
304/*******************************************************************************
305*
306* @brief This function write Status Register.
307*
308* @param reg SPI base address
309* @param cs 32-bit bitwise chip select setting
310* @param data 8-bit data
311*
312******************************************************************************/
314{
315 spi_instance_t *inst = flash->inst;
316 spi_select(inst,flash->cs);
317 spi_write(inst, flash->cmd_wr_status); //Write Status Register
318 spi_write(inst, data); //Write Status Register
319 spi_deselect(inst,flash->cs);
320}
321
322void spiFlash_f2m_single(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
323{
324 spi_select(flash->inst,flash->cs);
325 spiFlash_f2m_single_(flash, flashAddress, memoryAddress, size);
326 spi_deselect(flash->inst,flash->cs);
327}
328
329void spiFlash_f2m_dual(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
330{
331 spi_select(flash->inst,flash->cs);
332 spiFlash_f2m_dual_(flash, flashAddress, memoryAddress, size);
333 spi_deselect(flash->inst,flash->cs);
334}
335
336void spiFlash_f2m_quad(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
337{
339 spi_select(flash->inst,flash->cs);
340 spiFlash_f2m_quad_(flash, flashAddress, memoryAddress, size);
341 spi_deselect(flash->inst,flash->cs);
342}
343
344
345/* -----------------------------------------------------------------------------*/
346/* Public API: Enablement Operation
347/* -----------------------------------------------------------------------------*/
348
350{
351 u8 status = 0;
352 spi_instance_t *inst = flash->inst;
353
354 // Set Write Enable Latch (WEL) by sending CMD-0x06
355 do {
356 spiFlash_enableWrite(flash);
357 status = spiFlash_readStatusReg(flash);
358 bsp_uDelay(1);
359 } while ((status & WEL_BIT) != WEL_BIT); // 0x02 is standard WEL bit
360
361 // Mask the existing Status Register Bit-Flip (Winbond/Macronix/ISIS)
362 if (flash->info->flags & FLAG_QE_ENABLE_VIA_SR) {
363 spiFlash_writeStatusReg(flash, status | flash->mask_qe);
364 do {
365 status = spiFlash_readStatusReg(flash);
366 bsp_uDelay(1);
367 } while ((status & flash->mask_qe) != flash->mask_qe);
368 }
369
370
371}
372
374{
375 u8 status = 0;
376 spi_instance_t *inst = flash->inst;
377
378 // Set Write Enable Latch (WEL) by sending CMD-0x06
379 do {
380 spiFlash_enableWrite(flash);
381 status = spiFlash_readStatusReg(flash);
382 bsp_uDelay(1);
383 } while ((status & WEL_BIT) != WEL_BIT); // 0x02 is standard WEL bit
384
385 spi_select(inst,flash->cs);
387 spi_deselect(inst,flash->cs);
388
389}
390
391
393{
394 spi_instance_t *inst = flash->inst;
395 spi_select(inst,flash->cs);
396 spi_write(inst, CMD_WRITE_ENABLE); // Write Enable Sequence
397 spi_deselect(inst,flash->cs);
398}
399
401{
402 spi_instance_t *inst = flash->inst;
403
404 if (flash->info->flags & FLAG_4BYTE_SUPPORT)
405 {
406 spi_waitUntilIdle(inst);
407 spi_select(inst,flash->cs);
408 spi_write(inst,flash->cmd_exit_4byte);
409 spi_deselect(inst,flash->cs);
410 spi_waitUntilIdle(inst);
411
412 return SPI_FLASH_OK;
413 }
414 else return SPI_FLASH_SKIP;
415
416}
417
419{
420 spi_instance_t *inst = flash->inst;
422 spi_select(inst,flash->cs);
424 spi_deselect(inst,flash->cs);
425}
426
428{
429 spi_instance_t *inst = flash->inst;
431 spi_select(inst,flash->cs);
433 spi_deselect(inst,flash->cs);
434}
435
437{
438 u8 out;
439 u16 timeout=0;
440 while(1)
441 {
442 bsp_uDelay(1*1000);
443 out = spiFlash_readStatusReg(flash);
444 if((out & 0x01) ==0x00)
445 return SPI_FLASH_OK;
446 timeout++;
447 //sector erase max=400ms
448 if(timeout >=400)
449 {
450 return SPI_FLASH_ERR; //Time out
451 }
452 }
453}
454
456{
457 spi_instance_t *inst = flash->inst;
459 spi_select(inst,flash->cs);
461 spi_write(inst, (flashAddress>>16)&0xFF);
462 spi_write(inst, (flashAddress>>8)&0xFF);
463 spi_write(inst, (flashAddress>>0)&0xFF);
464 spi_deselect(inst,flash->cs);
465 spiFlash_waitBusy(flash);
466}
467
468/* -----------------------------------------------------------------------------*/
469/* Internal: Read/Write Operation
470/* -----------------------------------------------------------------------------*/
471
472static void spiFlash_f2m_single_(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size){
473 spi_instance_t *inst = flash->inst;
475 spi_write(inst, flashAddress >> 16);
476 spi_write(inst, flashAddress >> 8);
477 spi_write(inst, flashAddress >> 0);
478 spi_write(inst, 0);
479 u8 *ram = (u8 *) memoryAddress;
480 for(u32 idx = 0;idx < size;idx++){
481 *ram++ = spi_read(inst);
482 }
483
484}
485
486static void spiFlash_f2m_dual_(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size){
487 spi_instance_t *inst = flash->inst;
489 spi_write(inst, flashAddress >> 16);
490 spi_write(inst, flashAddress >> 8);
491 spi_write(inst, flashAddress >> 0);
492 spi_write(inst, 0);
493 spi_waitUntilIdle(inst);
495 u8 *ram = (u8 *) memoryAddress;
496 for(u32 idx = 0;idx < size;idx++){
497 *ram++ = spi_read(inst);
498 }
499 spi_setDataMode(inst,FULL_DUPLEX_SINGLE_LINE);// change mode back to single data mode
500}
501
502static void spiFlash_f2m_quad_(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size){
503 spi_instance_t *inst = flash->inst;
505 spi_write(inst, flashAddress >> 16);
506 spi_write(inst, flashAddress >> 8);
507 spi_write(inst, flashAddress >> 0);
508 spi_write(inst, 0);
509 spi_waitUntilIdle(inst);
510 spi_setDataMode(inst, HALF_DUPLEX_QUAD_LINE); // change mode to quad data mode
511 uint8_t *ram = (uint8_t *) memoryAddress;
512 for(u32 idx = 0;idx < size;idx++){
513 *ram++ = spi_read(inst);
514 }
515 spi_setDataMode(inst, FULL_DUPLEX_SINGLE_LINE); // change mode back to single data mode
516}
517
Board Support Package API definitions.
#define bsp_uDelay(usec)
Microsecond delay function using CLINT timer.
Definition bsp.h:84
#define LOG_WARN(mod, fmt,...)
Log a warning message (yellow).
Definition debug.h:245
#define LOG_INFO(mod, fmt,...)
Log an informational message (green).
Definition debug.h:233
#define LOG_ERR(mod, fmt,...)
Log an error message (red).
Definition debug.h:257
#define DBG_MOD_SPI_FLASH
SPI Flash driver.
Definition debug.h:143
#define DBG_MOD_RTC
Real-Time Clock driver.
Definition debug.h:144
const spiFlash_info_t known_flash[]
Internal table of factory-supported SPI Flash devices.
@ FULL_DUPLEX_SINGLE_LINE
Full-duplex mode using single data lin.
Definition spi.h:142
@ HALF_DUPLEX_QUAD_LINE
Half-duplex mode using quad data lin.
Definition spi.h:144
@ HALF_DUPLEX_DUAL_LINE
Half-duplex mode using dual data lin.
Definition spi.h:143
@ LOW
Clock is low when id.
Definition spi.h:149
@ DATA_SAMPLED_RISE_EDGE
Data sampled on rising clock ed.
Definition spi.h:155
#define FLAG_QE_ENABLE_VIA_SR
Check if QE requires a Status Register Write.
#define FLAG_QE_SR1_BIT6
Method B: Macronix/ISSI Style (Status Register 1).
#define FLAG_4BYTE_EXIT_ISSI
Quirk: ISSI-Specific 4-Byte Exit.
#define FLAG_UNLOCK_ON_PROBE
Quirk: Auto-Lock on Power Up.
#define FLAG_4BYTE_SUPPORT
Supports 4-Byte Addressing Mode.
spiFlash_status_t
SPI Flash transfer mode configuration.
Definition spiFlash.h:199
@ SPI_FLASH_OK
Successful Operation.
Definition spiFlash.h:200
@ SPI_FLASH_ERR
Unknown JEDEC ID, Electrical failure (0x00/0xFF).
Definition spiFlash.h:201
@ SPI_FLASH_SKIP
Skip the function.
Definition spiFlash.h:202
u8 spiFlash_write_single(spiFlash_instance_t *flash, u32 flashAddress, u8 *src, u32 len)
Write N byte to Flash using standard write mode via single Data Line.
Definition spiFlash.c:249
void spiFlash_writeStatusReg(spiFlash_instance_t *flash, u8 data)
Write Status Register.
Definition spiFlash.c:313
void spiFlash_eraseSector(spiFlash_instance_t *flash, u32 flashAddress)
Erases a sector of the SPI flash given an address.
Definition spiFlash.c:455
void spiFlash_f2m_dual(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
This function read data from FlashAddress and copy to memoryAddress of specific size with dual data l...
Definition spiFlash.c:329
void spiFlash_enableQPI(spiFlash_instance_t *flash)
Set Write Enable Latch and send CMD 0x38 to enable QPI Mode.
Definition spiFlash.c:373
spiFlash_status_t spiFlash_probe(spiFlash_instance_t *flash)
Main wrapper function to initialize the SPI Flash.
Definition spiFlash.c:62
void spiFlash_unlockGlobal(spiFlash_instance_t *flash)
Globally unlocks the SPI flash.
Definition spiFlash.c:427
void spiFlash_applyConfig(spiFlash_instance_t *flash)
Apply stored SPI Flash configuration to hardware.
Definition spiFlash.c:94
spiFlash_status_t spiFlash_verify(spiFlash_instance_t *flash)
Verify spiFlash.
Definition spiFlash.c:164
spiFlash_status_t spiFlash_waitBusy(spiFlash_instance_t *flash)
Wait for spiFlash to be free.
Definition spiFlash.c:436
u8 spiFlash_readId(spiFlash_instance_t *flash)
Select and Read Device ID from spiFlash.
Definition spiFlash.c:125
void spiFlash_read_single(spiFlash_instance_t *flash, u32 flashAddress, u8 *buffer, u32 len)
Read N byte from Flash using standard read mode via single Data Line.
Definition spiFlash.c:270
u8 spiFlash_readStatusReg(spiFlash_instance_t *flash)
Read Status Register.
Definition spiFlash.c:294
void spiFlash_f2m_quad(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
This function read data from FlashAddress and copy to memoryAddress of specific size with quad data l...
Definition spiFlash.c:336
void spiFlash_applyQuirks(spiFlash_instance_t *flash)
Handle those spiFlash that have unique register/way.
Definition spiFlash.c:189
u8 spiFlash_exit4ByteAddr(spiFlash_instance_t *flash)
Exit 4-byte addressing.
Definition spiFlash.c:400
void spiFlash_enableWrite(spiFlash_instance_t *flash)
Set Write Enable Latch (WEL) to 1.
Definition spiFlash.c:392
u32 spiFlash_readJedecId(spiFlash_instance_t *flash)
Select and read JEDEC ID from spiFlash.
Definition spiFlash.c:134
const spiFlash_info_t * spiFlash_lookup(u32 detected_id)
Identify SPI Flash by looking up User Flash Table and known flash table.
Definition spiFlash.c:143
void spiFlash_lockGlobal(spiFlash_instance_t *flash)
Globally locks the SPI flash.
Definition spiFlash.c:418
void spiFlash_enableQuadMode(spiFlash_instance_t *flash)
Set Write Enable Latch and set Quad Enable bit to enable Quad Mode.
Definition spiFlash.c:349
void spiFlash_f2m_single(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
This function read data from FlashAddress and copy to memoryAddress of specific size with single data...
Definition spiFlash.c:322
void spiFlash_registerFlash(const spiFlash_info_t *table, size_t count)
Register Custom Flash to the driver.
Definition spiFlash.c:27
void spiFlash_wake(spiFlash_instance_t *flash)
Select spi and wake up SPI Flash.
Definition spiFlash.c:100
void spiFlash_initController(spiFlash_instance_t *flash)
Initialize SPI setting.
Definition spiFlash.c:33
#define CMD_ENABLE_QPI
To enable Quad Mode, need to write to this register for (*GigaDevice Quirk).
Definition spiFlash.h:149
#define CMD_PAGE_PROGRAM
Standard Write Page (256 Bytes).
Definition spiFlash.h:122
#define CMD_READ_STATUS_REG_1
Standard Read Status Register 1 (WIP, WEL, BP).
Definition spiFlash.h:109
#define CMD_SECTOR_ERASE
Standard Erase 4KB Sector.
Definition spiFlash.h:165
#define CMD_GLOBAL_UNLOCK
Standard Global Block Unlock.
Definition spiFlash.h:148
#define QE_BIT6
This Macro specifically for Macronix & ISIS Flash to enable Quad Mode.
Definition spiFlash.h:174
#define CMD_WRITE_STATUS_REG_1
Standard Write SR1 (Macronix/ISSI/Standard).
Definition spiFlash.h:112
#define CMD_GLOBAL_LOCK
Standard Global Block Lock.
Definition spiFlash.h:147
#define CMD_READ_DATA
Standard Read (up to 33MHz).
Definition spiFlash.h:133
#define CMD_FAST_READ
Standard Read at higher speed.
Definition spiFlash.h:134
#define CMD_READ_DEVICE_ID
Standard Read device ID (legacy).
Definition spiFlash.h:101
#define CMD_EXIT_4B_ISSI
Exit 4-Byte Mode (*ISSI Quirk).
Definition spiFlash.h:160
#define CMD_WRITE_ENABLE
Standard Set WEL Bit.
Definition spiFlash.h:124
#define CMD_DUAL_OUTPUT_READ
Standard Double throughput in read mode.
Definition spiFlash.h:135
#define CMD_QUAD_OUTPUT_READ
Standard Quad throughput in read mode.
Definition spiFlash.h:136
#define CMD_EXIT_4B
Standard Exit 4-Byte Mode (Standard).
Definition spiFlash.h:159
#define CMD_READ_JEDEC_ID
Standard Read JEDEC ID (Manuf + Type + Cap).
Definition spiFlash.h:100
#define CMD_RELEASE_DEEP_POWER_DOWN
Standard Release flash from deep power down.
Definition spiFlash.h:144
#define WEL_BIT
Write Enable Latch Bit in Status Reg.
Definition spiFlash.h:176
u8 spi_read(spi_instance_t *inst)
Reads an 8-bit data value from the SPI read register.
Definition spi.c:71
void spi_waitUntilIdle(spi_instance_t *inst)
Waits for SPI if it has any command waiting to be executed in queue.
Definition spi.c:150
void spi_applyConfig(spi_instance_t *inst)
Applies the current configuration settings stored in the spi_instance_t structure to the SPI hardware...
Definition spi.c:93
void spi_write(spi_instance_t *inst, u8 data)
Writes an 8-bit data value to the SPI data register.
Definition spi.c:105
void spi_deselect(spi_instance_t *inst, u32 cs)
Deselects the SPI slave by deasserting the corresponding chip select (CS) line.
Definition spi.c:132
void spi_setDataMode(spi_instance_t *inst, enum cfg_mode mode)
Set SPI Data Mode (Full/Half Duplex, Dual/Quad Line).
Definition spi.c:25
void spi_select(spi_instance_t *inst, u32 cs)
Selects the SPI slave by asserting the corresponding chip select (CS) line.
Definition spi.c:123
SPI Flash driver API definitions.
SPI instance. Holds the software registers and hardware pointer.
Definition spi.h:236
enum cfg_mode mode
Stored Transfer Mode.
Definition spi.h:240
u32 ssSetup
Slave Select Setup Cycles.
Definition spi.h:242
u32 clkDivider
Clock Divider Value.
Definition spi.h:241
enum cfg_cpol cpol
Stored Clock Polarity.
Definition spi.h:238
enum cfg_cpha cpha
Stored Clock Phase.
Definition spi.h:239
u32 ssHold
Slave Select Hold Cycles.
Definition spi.h:243
u32 ssDisable
Slave Select Disable Cycles.
Definition spi.h:244
SPI Flash Device Descriptor.
const char * part_no
String representation of Part Number (e.g., "W25Q128").
flash_hook post_init_hook
Optional callback (NULL if unused).
u32 flags
Capability Flags (Flash Capability Flags).
SPI Flash instance structure.
Definition spiFlash.h:232
u8 cs
Chip select.
Definition spiFlash.h:236
u32 detected_id
JEDEC_ID = Manu_id, mem_type, capacity.
Definition spiFlash.h:235
u8 cmd_exit_4byte
CMD for exit 4 byte addressing.
Definition spiFlash.h:241
u8 mask_qe
CMD for Quad Enable Bit.
Definition spiFlash.h:242
u8 cmd_wr_status
CMD for Write Status.
Definition spiFlash.h:240
const spiFlash_info_t * info
Flash Descriptor.
Definition spiFlash.h:234
u8 cmd_rd_status
CMD for Read Status.
Definition spiFlash.h:239
spi_instance_t * inst
Pointer to shared SPI Master.
Definition spiFlash.h:233
uint8_t u8
Definition type.h:30
uint16_t u16
Definition type.h:28
uint32_t u32
Definition type.h:26