57 flash-> mask_qe = 0x0;
63 spiFlash_applyQuirks(flash);
79 spiFlash_wake_(flash);
151 for (
int i = 0; i < 2; i++) {
152 if (tables[i] != NULL) {
155 "User flash is not found/match, checking with known flash.");
156 if (flash->
info != NULL)
break;
160 if (flash->
info == NULL) {
176 u8 data = spiFlash_read_id_(flash);
197 if (table == NULL)
return NULL;
199 for (
int i = 0; table[i].
part_no != NULL; i++) {
200 if (table[i].jedec_id == detected_id) {
244 spi_write(inst, (flashAddress>>16) & 0xFF);
245 spi_write(inst, (flashAddress>>8) & 0xFF);
246 spi_write(inst, (flashAddress>>0) & 0xFF);
247 for(
int i=0; i<len; i++)
266 spi_write(inst, (flashAddress>>16) & 0xFF);
267 spi_write(inst, (flashAddress>>8) & 0xFF);
268 spi_write(inst, (flashAddress>>0) & 0xFF);
269 for(
int i=0; i<len; i++)
284 spi_write(inst, (flashAddress>>16) & 0xFF);
285 spi_write(inst, (flashAddress>>8) & 0xFF);
286 spi_write(inst, (flashAddress>>0) & 0xFF);
287 for (
u32 i = 0; i < len; i++)
299 spi_write(inst, (flashAddress >> 16) & 0xFF);
300 spi_write(inst, (flashAddress >> 8) & 0xFF);
301 spi_write(inst, (flashAddress >> 0) & 0xFF);
305 for (
u32 i = 0; i < len; i++)
352 spiFlash_f2m_(flash, flashAddress, memoryAddress, size);
359 spiFlash_dual_f2m_(flash, flashAddress, memoryAddress, size);
366 spiFlash_quad_f2m_(flash, flashAddress, memoryAddress, size);
457 if((out & 0x01) ==0x00)
474 spi_write(inst, (flashAddress>>16)&0xFF);
492 u8 *ram = (
u8 *) memoryAddress;
493 for(
u32 idx = 0;idx < size;idx++){
508 u8 *ram = (
u8 *) memoryAddress;
509 for(
u32 idx = 0;idx < size;idx++){
525 uint8_t *ram = (uint8_t *) memoryAddress;
526 for(
u32 idx = 0;idx < size;idx++){
#define LOG_WARN(debug, fmt,...)
#define LOG_INFO(debug, fmt,...)
#define LOG_ERR(debug, fmt,...)
#define DBG_MOD_SPI_FLASH
SPI Flash Driver.
#define DBG_MOD_RTC
Real Time Clock.
const spiFlash_info_t known_flash[]
Supported Flash Info.
@ FULL_DUPLEX_SINGLE_LINE
Full-duplex mode using single data lin.
@ HALF_DUPLEX_QUAD_LINE
Half-duplex mode using quad data lin.
@ HALF_DUPLEX_DUAL_LINE
Half-duplex mode using dual data lin.
@ LOW
Clock is low when id.
@ DATA_SAMPLED_RISE_EDGE
Data sampled on rising clock ed.
#define FLAG_QE_ENABLE_VIA_SR
Check if QE requires a Status Register Write.
#define FLAG_QE_SR1_BIT6
Method B: Macronix/ISSI Style (Status Register 1).
#define FLAG_QE_SR2_BIT1
Method A: Winbond Style (Status Register 2).
#define FLAG_4BYTE_EXIT_ISSI
Quirk: ISSI-Specific 4-Byte Exit.
#define FLAG_UNLOCK_ON_PROBE
Quirk: Auto-Lock on Power Up.
#define FLAG_4BYTE_SUPPORT
Supports 4-Byte Addressing Mode.
#define FLAG_QE_CMD_38
Method C: GigaDevice Command.
spiFlash_status_t
SPI Flash transfer mode configuration.
@ SPI_FLASH_OK
Successful Operation */.
@ SPI_FLASH_ERR
Unknown JEDEC ID, Electrical failure (0x00/0xFF) */.
@ SPI_FLASH_SKIP
Skip the function */.
void spiFlash_writeStatusReg(spiFlash_instance_t *flash, u8 data)
Write Status Register.
void spiFlash_read_quad(spiFlash_instance_t *flash, u32 flashAddress, u8 *buffer, u32 len)
Read N byte from Flash using quad read mode.
void spiFlash_writeEnable(spiFlash_instance_t *flash)
Set Write Enable Latch.
spiFlash_status_t spiFlash_verify(spiFlash_instance_t *flash, const spiFlash_info_t *user_flash)
Verify spiFlash.
void spiFlash_sectorErase(spiFlash_instance_t *flash, u32 flashAddress)
Erases a sector of the SPI flash given an address.
u32 spiFlash_jedec_id(spiFlash_instance_t *flash)
Select and read JEDEC ID from spiFlash.
u8 spiFlash_read_id(spiFlash_instance_t *flash)
Select and Read Device ID from spiFlash.
void spiFlash_read(spiFlash_instance_t *flash, u32 flashAddress, u8 *buffer, u32 len)
Read N byte from Flash using standard read mode.
void spiFlash_enable_quad_access(spiFlash_instance_t *flash)
Set Write Enable Latch and set Quad Enable bit to enable Quad SPI.
spiFlash_status_t spiFlash_waitBusy(spiFlash_instance_t *flash)
Wait for spiFlash to be free.
u8 spiFlash_write_quad(spiFlash_instance_t *flash, u32 flashAddress, u8 *src, u32 len)
Write N byte to Flash using quad write mode.
u8 spiFlash_readStatusReg(spiFlash_instance_t *flash)
Read Status Register.
void spiFlash_globalUnlock(spiFlash_instance_t *flash)
Globally unlocks the SPI flash.
u8 spiFlash_write(spiFlash_instance_t *flash, u32 flashAddress, u8 *src, u32 len)
Write N byte to Flash using standard write mode.
u8 spiFlash_exit4ByteAddr(spiFlash_instance_t *flash)
Exit 4-byte addressing.
void spiFlash_f2m(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
This function read data from FlashAddress and copy to memoryAddress of specific size with single data...
void spiFlash_init_controller(spiFlash_instance_t *flash)
Initialize SPI setting.
void spiFlash_globalLock(spiFlash_instance_t *flash)
Globally locks the SPI flash.
spiFlash_status_t spiFlash_probe(spiFlash_instance_t *flash, const spiFlash_info_t *user_flash)
The main wrapper for initialize SPI Flash.
void spiFlash_wake(spiFlash_instance_t *flash)
Select spi and wake up SPI Flash.
#define QE_BIT1
This Macro specifically for Windbond Flash to enable Quad Mode **/.
#define CMD_PAGE_PROGRAM
Standard Write Page (256 Bytes) **/.
#define CMD_READ_STATUS_REG_1
Standard Read Status Register 1 (WIP, WEL, BP) **/.
#define CMD_SECTOR_ERASE
Standard Erase 4KB Sector **/.
#define CMD_GLOBAL_UNLOCK
Standard Global Block Unlock **/.
#define CMD_ENABLE_QUAD_GD
To enable Quad Mode, need to write to this register for (*GigaDevice Quirk) **/.
#define QE_BIT6
This Macro specifically for Macronix & ISIS Flash to enable Quad Mode **/.
#define CMD_QUAD_PAGE_PROGRAM
Standard Write Page (256 Bytes) **/.
#define CMD_WRITE_STATUS_REG_1
Standard Write SR1 (Macronix/ISSI/Standard) **/.
#define CMD_GLOBAL_LOCK
Standard Global Block Lock **/.
#define CMD_READ_DATA
Standard Read (up to 33MHz) **/.
#define CMD_FAST_READ
Standard Read at higher speed **/.
#define CMD_READ_DEVICE_ID
Standard Read device ID (legacy) **/.
#define CMD_READ_STATUS_REG_2
Read Status Register 2 (*QE for Winbond) **/.
#define CMD_EXIT_4B_ISSI
Exit 4-Byte Mode (*ISSI Quirk) **/.
#define CMD_WRITE_ENABLE
Standard Set WEL Bit **/.
#define CMD_DUAL_OUTPUT_READ
Standard Double throughput in read mode.**/.
#define CMD_QUAD_OUTPUT_READ
Standard Quad throughput in read mode.**/.
#define CMD_EXIT_4B
Standard Exit 4-Byte Mode (Standard) **/.
#define CMD_WRITE_STATUS_REG_2
Write SR2 (*Winbond Specific Quirk) **/.
#define CMD_READ_JEDEC_ID
Standard Read JEDEC ID (Manuf + Type + Cap) **/.
#define CMD_RELEASE_DEEP_POWER_DOWN
Standard Release flash from deep power down. */.
#define WEL_BIT
Write Enable Latch Bit in Status Reg **/.
u8 spi_read(spi_instance_t *inst)
Reads an 8-bit data value from the SPI read register.
void spi_waitUntilIdle(spi_instance_t *inst)
Waits for SPI if it has any command waiting to be executed in queue.
void spi_diselect(spi_instance_t *inst, u32 cs)
Deselects the SPI slave by deasserting the corresponding chip select (CS) line.
void spi_applyConfig(spi_instance_t *inst)
Applies the current configuration settings stored in the spi_instance_t structure to the SPI hardware...
void spi_write(spi_instance_t *inst, u8 data)
Writes an 8-bit data value to the SPI data register.
void spi_setDataMode(spi_instance_t *inst, enum cfg_mode Mode)
Set SPI Data Mode (Full/Half Duplex, Dual/Quad Line).
void spi_select(spi_instance_t *inst, u32 cs)
Selects the SPI slave by asserting the corresponding chip select (CS) line.
void spiFlash_f2m_dual(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
void spiFlash_f2m_quad(spiFlash_instance_t *flash, u32 flashAddress, uintptr_t memoryAddress, u32 size)
SPI Flash driver API definitions.
SPI instance. Holds the software registers and hardware pointer.
enum cfg_mode mode
Stored Transfer Mode.
u32 ssSetup
Slave Select Setup Cycles.
u32 clkDivider
Clock Divider Value.
enum cfg_cpol cpol
Stored Clock Polarity.
enum cfg_cpha cpha
Stored Clock Phase.
u32 ssHold
Slave Select Hold Cycles.
u32 ssDisable
Slave Select Disable Cycles.
SPI Flash Device Descriptor.
flash_hook post_init_hook
SPI Flash instance structure.
u32 detected_id
JEDEC_ID = Manu_id, mem_type, capacity */.
u8 cmd_exit_4byte
CMD for exit 4 byte addressing */.
u8 mask_qe
CMD for Quad Enable Bit */.
u8 cmd_wr_status
CMD for Write Status */.
const spiFlash_info_t * info
Flash Descriptor */.
u8 cmd_rd_status
CMD for Read Status */.
spi_instance_t * inst
Pointer to shared SPI Master */.