Standard SPI Flash command definitions.
ID & Discovery | |
Standard SPI Flash Identification Commands.
| |
| #define | CMD_READ_JEDEC_ID 0x9F |
| Standard Read JEDEC ID (Manuf + Type + Cap). | |
| #define | CMD_READ_DEVICE_ID 0xAB |
| Standard Read device ID (legacy). | |
Status Register Commands | |
Standard SPI Flash Status Register Commands.
| |
| #define | CMD_READ_STATUS_REG_1 0x05 |
| Standard Read Status Register 1 (WIP, WEL, BP). | |
| #define | CMD_READ_STATUS_REG_2 0x35 |
| Read Status Register 2 (*QE for Winbond). | |
| #define | CMD_READ_STATUS_REG_3 0x15 |
| Read Status Register 3 (*Winbond). | |
| #define | CMD_WRITE_STATUS_REG_1 0x01 |
| Standard Write SR1 (Macronix/ISSI/Standard). | |
| #define | CMD_WRITE_STATUS_REG_2 0x31 |
| Write SR2 (*Winbond Specific Quirk). | |
| #define | CMD_WRITE_STATUS_REG_3 0x11 |
| Write SR3. | |
Standard Write Commands | |
Standard SPI Flash Standard Commands.
| |
| #define | CMD_PAGE_PROGRAM 0x02 |
| Standard Write Page (256 Bytes). | |
| #define | CMD_QUAD_PAGE_PROGRAM 0x32 |
| Standard Write Page (256 Bytes). | |
| #define | CMD_WRITE_ENABLE 0x06 |
| Standard Set WEL Bit. | |
| #define | CMD_WRITE_DISABLE 0x04 |
| Standard Clear WEL Bit. | |
Standard Read Commands | |
Standard SPI Flash Read Commands.
| |
| #define | CMD_READ_DATA 0x03 |
| Standard Read (up to 33MHz). | |
| #define | CMD_FAST_READ 0x0B |
| Standard Read at higher speed. | |
| #define | CMD_DUAL_OUTPUT_READ 0x3B |
| Standard Double throughput in read mode. | |
| #define | CMD_QUAD_OUTPUT_READ 0x6B |
| Standard Quad throughput in read mode. | |
Standard Misc Commands | |
Standard SPI Flash Standard Commands.
| |
| #define | CMD_RELEASE_DEEP_POWER_DOWN 0xAB |
| Standard Release flash from deep power down. | |
| #define | CMD_ENABLE_RESET 0x66 |
| Standard Reset Enable. | |
| #define | CMD_RESET_DEVICE 0x99 |
| Standard Trigger Reset. | |
| #define | CMD_GLOBAL_LOCK 0x7E |
| Standard Global Block Lock. | |
| #define | CMD_GLOBAL_UNLOCK 0x98 |
| Standard Global Block Unlock. | |
| #define | CMD_ENABLE_QPI 0x38 |
| To enable Quad Mode, need to write to this register for (*GigaDevice Quirk). | |
Standard 4-Byte Addressing Commands | |
Standard SPI Flash 4-Byte Addressing Commands.
| |
| #define | CMD_ENTER_4B 0xB7 |
| Standard Enter 4-Byte Mode (Stateful). | |
| #define | CMD_EXIT_4B 0xE9 |
| Standard Exit 4-Byte Mode (Standard). | |
| #define | CMD_EXIT_4B_ISSI 0x29 |
| Exit 4-Byte Mode (*ISSI Quirk). | |
| #define | CMD_DUAL_OUTPUT_READ_4B 0x3C |
| Standard Double throughput in read mode, 4-byte Mode. | |
| #define | CMD_QUAD_OUTPUT_READ_4B 0x6C |
| Standard Quad throughput in read mode, 4-byte Mode. | |
| #define | CMD_READ_4B 0x13 |
| Standard Read Data with 32-bit Address. | |
| #define | CMD_PROGRAM_4B 0x12 |
| Standard Page Program with 32-bit Address. | |
| #define | CMD_SECTOR_ERASE 0x20 |
| Standard Erase 4KB Sector. | |
| #define | CMD_ERASE_4K_4B 0x21 |
| Standard Sector Erase with 32-bit Address. | |
| #define | CMD_ERASE_64K_4B 0xDC |
| Standard Block Erase with 32-bit Address. | |
Misc Macros | |
Standard SPI Flash Miscellaneous Macros. | |
| #define | QE_BIT6 0x40 |
| This Macro specifically for Macronix & ISIS Flash to enable Quad Mode. | |
| #define | QE_BIT1 0x02 |
| This Macro specifically for Windbond Flash to enable Quad Mode. | |
| #define | WEL_BIT 0x02 |
| Write Enable Latch Bit in Status Reg. | |
| #define CMD_DUAL_OUTPUT_READ 0x3B |
#include <spiFlash.h>
Standard Double throughput in read mode.
Definition at line 135 of file spiFlash.h.
| #define CMD_DUAL_OUTPUT_READ_4B 0x3C |
#include <spiFlash.h>
Standard Double throughput in read mode, 4-byte Mode.
Definition at line 161 of file spiFlash.h.
| #define CMD_ENABLE_QPI 0x38 |
#include <spiFlash.h>
To enable Quad Mode, need to write to this register for (*GigaDevice Quirk).
Definition at line 149 of file spiFlash.h.
| #define CMD_ENABLE_RESET 0x66 |
| #define CMD_ENTER_4B 0xB7 |
#include <spiFlash.h>
Standard Enter 4-Byte Mode (Stateful).
Definition at line 158 of file spiFlash.h.
| #define CMD_ERASE_4K_4B 0x21 |
#include <spiFlash.h>
Standard Sector Erase with 32-bit Address.
Definition at line 166 of file spiFlash.h.
| #define CMD_ERASE_64K_4B 0xDC |
#include <spiFlash.h>
Standard Block Erase with 32-bit Address.
Definition at line 167 of file spiFlash.h.
| #define CMD_EXIT_4B 0xE9 |
#include <spiFlash.h>
Standard Exit 4-Byte Mode (Standard).
Definition at line 159 of file spiFlash.h.
| #define CMD_EXIT_4B_ISSI 0x29 |
| #define CMD_FAST_READ 0x0B |
| #define CMD_GLOBAL_LOCK 0x7E |
| #define CMD_GLOBAL_UNLOCK 0x98 |
| #define CMD_PAGE_PROGRAM 0x02 |
| #define CMD_PROGRAM_4B 0x12 |
#include <spiFlash.h>
Standard Page Program with 32-bit Address.
Definition at line 164 of file spiFlash.h.
| #define CMD_QUAD_OUTPUT_READ 0x6B |
#include <spiFlash.h>
Standard Quad throughput in read mode.
Definition at line 136 of file spiFlash.h.
| #define CMD_QUAD_OUTPUT_READ_4B 0x6C |
#include <spiFlash.h>
Standard Quad throughput in read mode, 4-byte Mode.
Definition at line 162 of file spiFlash.h.
| #define CMD_QUAD_PAGE_PROGRAM 0x32 |
| #define CMD_READ_4B 0x13 |
#include <spiFlash.h>
Standard Read Data with 32-bit Address.
Definition at line 163 of file spiFlash.h.
| #define CMD_READ_DATA 0x03 |
| #define CMD_READ_DEVICE_ID 0xAB |
| #define CMD_READ_JEDEC_ID 0x9F |
#include <spiFlash.h>
Standard Read JEDEC ID (Manuf + Type + Cap).
Definition at line 100 of file spiFlash.h.
| #define CMD_READ_STATUS_REG_1 0x05 |
#include <spiFlash.h>
Standard Read Status Register 1 (WIP, WEL, BP).
Definition at line 109 of file spiFlash.h.
| #define CMD_READ_STATUS_REG_2 0x35 |
#include <spiFlash.h>
Read Status Register 2 (*QE for Winbond).
Definition at line 110 of file spiFlash.h.
| #define CMD_READ_STATUS_REG_3 0x15 |
| #define CMD_RELEASE_DEEP_POWER_DOWN 0xAB |
#include <spiFlash.h>
Standard Release flash from deep power down.
Definition at line 144 of file spiFlash.h.
| #define CMD_RESET_DEVICE 0x99 |
| #define CMD_SECTOR_ERASE 0x20 |
| #define CMD_WRITE_DISABLE 0x04 |
| #define CMD_WRITE_ENABLE 0x06 |
| #define CMD_WRITE_STATUS_REG_1 0x01 |
#include <spiFlash.h>
Standard Write SR1 (Macronix/ISSI/Standard).
Definition at line 112 of file spiFlash.h.
| #define CMD_WRITE_STATUS_REG_2 0x31 |
#include <spiFlash.h>
Write SR2 (*Winbond Specific Quirk).
Definition at line 113 of file spiFlash.h.
| #define CMD_WRITE_STATUS_REG_3 0x11 |
| #define QE_BIT1 0x02 |
#include <spiFlash.h>
This Macro specifically for Windbond Flash to enable Quad Mode.
Definition at line 175 of file spiFlash.h.
| #define QE_BIT6 0x40 |
#include <spiFlash.h>
This Macro specifically for Macronix & ISIS Flash to enable Quad Mode.
Definition at line 174 of file spiFlash.h.
| #define WEL_BIT 0x02 |
#include <spiFlash.h>
Write Enable Latch Bit in Status Reg.
Definition at line 176 of file spiFlash.h.