cfg_mode
SPI transfer mode configuration.
u8 spi_read(spi_instance_t *inst)
Reads an 8-bit data value from the SPI read register.
u32 spi_read32(spi_instance_t *inst)
Reads a 32-bit data value from the SPI read register.
void spi_waitUntilIdle(spi_instance_t *inst)
Waits for SPI if it has any command waiting to be executed in queue.
void spi_diselect(spi_instance_t *inst, u32 cs)
Deselects the SPI slave by deasserting the corresponding chip select (CS) line.
u32 spi_isBusy(spi_instance_t *inst)
Check SPI if it has any command waiting to be executed in queue.
void spi_applyConfig(spi_instance_t *inst)
Applies the current configuration settings stored in the spi_instance_t structure to the SPI hardware...
void spi_write(spi_instance_t *inst, u8 data)
Writes an 8-bit data value to the SPI data register.
u32 spi_writeRead32(spi_instance_t *inst, u32 data)
Writes data to and reads data from the SPI data register.
u32 spi_cmdAvailability(spi_instance_t *inst)
Returns the availability of command buffer space in the SPI buffer.
u8 spi_writeRead(spi_instance_t *inst, u8 data)
Writes data to and reads data from the SPI data register.
void spi_write32(spi_instance_t *inst, u32 data)
Writes a 32-bit data value to the SPI data register.
u32 spi_rspOccupancy(spi_instance_t *inst)
Returns the occupancy of the response buffer in the SPI buffer.
void spi_setDataMode(spi_instance_t *inst, enum cfg_mode Mode)
Set SPI Data Mode (Full/Half Duplex, Dual/Quad Line).
void spi_select(spi_instance_t *inst, u32 cs)
Selects the SPI slave by asserting the corresponding chip select (CS) line.
#define SPI_CMD_RD
Read Trigger.
#define SPI_CMD_SS
Slave Select Trigger.
#define SPI_CMD_WR
Write Trigger.
#define SPI_CMD_VALID
Command Valid S.
SPI driver API definitions.
u32 SSSETUP
Address Offset: 0x24 - SS Setup Cycles.
u32 CMD
Address Offset: 0x00 - Command Register.
u32 INTERRUPT
Address Offset: 0x0C - Interrupt Control.
u32 CMD_WRITELARGE
Address Offset: 0x50 - 32-bit Write.
u32 SSDISABLE
Address Offset: 0x2C - SS Disable Cycles.
u32 CMD_READLARGE
Address Offset: 0x58 - 32-bit Read.
u32 RSP
Address Offset: 0x04 - Response Register.
u32 CONFIG
Address Offset: 0x08 - Configuration Register.
u32 CLOCKDIVIDER
Address Offset: 0x20 - Clock Divider.
u32 SSHOLD
Address Offset: 0x28 - SS Hold Cycles.
u32 CMD_READWRITELARGE
Address Offset: 0x54 - 32-bit Read/Write.
SPI instance. Holds the software registers and hardware pointer.
spi_hwreg_t * hwreg
Pointer to Hardware Register Map.
enum cfg_mode mode
Stored Transfer Mode.
u32 ssSetup
Slave Select Setup Cycles.
u32 clkDivider
Clock Divider Value.
enum cfg_cpol cpol
Stored Clock Polarity.
enum cfg_cpha cpha
Stored Clock Phase.
u32 ssHold
Slave Select Hold Cycles.
u32 ssDisable
Slave Select Disable Cycles.