spi.h

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// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
// Full license header: bsp/efinix/EfxSapphireSocRV64/include/LICENSE.MD
 
#ifndef SPI_H
#define SPI_H

 
#include <stdint.h>
#include "type.h"
#include "soc.h"
 
#ifdef __cplusplus
extern "C" {
#endif

 
/* ========================================================================== */
/* SUB-GROUP : REGISTER DEFINITIONS                                          */
/* ========================================================================== */


    #define SPI_CMD_DATA_MASK           0xFF      
    #define SPI_CMD_WR                  (1 << 8)  
    #define SPI_CMD_RD                  (1 << 9)  
    #define SPI_CMD_SS                  (1 << 11) 
    #define SPI_CMD_READ_INVALID        (1 << 31) 

    #define SPI_RSP_CMD_FIFO_AVAILABILITY (0xFFFF)       
    #define SPI_RSP_FIFO_OCCUPANCY        (0xFFFF << 16) 

    #define SPI_CONFIG_CPOL             (1 << 0)  
    #define SPI_CONFIG_MODE             (1 << 4)  
    #define SPI_CONFIG_CPHA             (1 << 16) 

    #define SPI_INTC_CMD_INT_ENABLE     (1 << 0)  
    #define SPI_INTC_RSP_INT_ENABLE     (1 << 1)  
    #define SPI_CMD_INT                 (1 << 8)  
    #define SPI_RSP_INT                 (1 << 9)  
    #define SPI_CMD_VALID               (1 << 16) 
 // End of SPI_Macros group
 

//-----------------------------------------------------------------------------
// SPI Hardware Sanity Check (Hidden from User)
//-----------------------------------------------------------------------------
#define IS_VALID_CPOL(x) ((x) == LOW || (x) == HIGH)
#define IS_VALID_CPHA(x) ((x) == DATA_SAMPLED_RISE_EDGE || (x) == DATA_SAMPLED_FALL_EDGE)
#define IS_VALID_MODE(x) ((x) == FULL_DUPLEX_SINGLE_LINE || (x) == HALF_DUPLEX_DUAL_LINE || (x) == HALF_DUPLEX_QUAD_LINE)
 
 
/* ========================================================================== */
/* SUB-GROUP : Data Types                                                    */
/* ========================================================================== */


        enum cfg_mode {
            FULL_DUPLEX_SINGLE_LINE = 0, 
            HALF_DUPLEX_DUAL_LINE = 1, 
            HALF_DUPLEX_QUAD_LINE = 2  
        };

        enum cfg_cpol {
            LOW  = 0, 
            HIGH = 1  
        };

        enum cfg_cpha {
            DATA_SAMPLED_RISE_EDGE = 0, 
            DATA_SAMPLED_FALL_EDGE = 1  
        };

 // End of SPI_ENUM group
 
/* ========================================================================== */
/* SUB-GROUP : DATA STRUCTS                                                     */
/* ========================================================================== */

    typedef volatile struct {
        u32 CMD;                
        u32 RSP;                
        u32 CONFIG;             
        u32 INTERRUPT;          
        u32 RESERVED0[4];       
        u32 CLOCKDIVIDER;       
        u32 SSSETUP;            
        u32 SSHOLD;             
        u32 SSDISABLE;          
        u32 SSACTIVEHIGH;       
        u32 RESERVED1[7];       
        u32 CMD_WRITELARGE;     
        u32 CMD_READWRITELARGE; 
        u32 CMD_READLARGE;      
    } spi_hwreg_t;
 

    typedef struct {
        spi_hwreg_t     *hwreg;       
        enum cfg_cpol   cpol;         
        enum cfg_cpha   cpha;         
        enum cfg_mode   mode;         
        u32             clkDivider;   
        u32             ssSetup;      
        u32             ssHold;       
        u32             ssDisable;    
    } spi_instance_t;
 // End of SPI_Types group
 
 
/* ========================================================================== */
/* SUB-GROUP: FUNCTIONS                                                     */
/* ========================================================================== */


    u8 spi_read(spi_instance_t *inst);

    u8 spi_writeRead(spi_instance_t *inst, u8 data);

    u32 spi_read32(spi_instance_t *inst);

    u32 spi_rspOccupancy(spi_instance_t *inst);

    u32 spi_cmdAvailability(spi_instance_t *inst);

    u32 spi_isBusy(spi_instance_t *inst);

    u32 spi_writeRead32(spi_instance_t *inst, u32 data);

    void spi_applyConfig(spi_instance_t *inst);

    void spi_waitUntilIdle(spi_instance_t *inst);

    void spi_write(spi_instance_t *inst, u8 data);

    void spi_write32(spi_instance_t *inst, u32 data);

    void spi_select(spi_instance_t *inst, u32 cs);

    void spi_diselect(spi_instance_t *inst, u32 cs);

    void spi_setDataMode(spi_instance_t *inst, enum cfg_mode mode);
 // End of SPI_Funcs group
 
#ifdef __cplusplus
}
#endif // C_plusplus
 // End of MAIN SPI Group
 
#endif // SPI_H