#include <spi.h>

Data Fields
u32	CMD
	Address Offset: 0x00 - Command Register.
u32	RSP
	Address Offset: 0x04 - Response Register.
u32	CONFIG
	Address Offset: 0x08 - Configuration Register.
u32	INTERRUPT
	Address Offset: 0x0C - Interrupt Control.
u32	RESERVED0 [4]
	Reserved.
u32	CLOCKDIVIDER
	Address Offset: 0x20 - Clock Divider.
u32	SSSETUP
	Address Offset: 0x24 - SS Setup Cycles.
u32	SSHOLD
	Address Offset: 0x28 - SS Hold Cycles.
u32	SSDISABLE
	Address Offset: 0x2C - SS Disable Cycles.
u32	SSACTIVEHIGH
	Address Offset: 0x30 - SS Polarity.
u32	RESERVED1 [7]
	Reserved.
u32	CMD_WRITELARGE
	Address Offset: 0x50 - 32-bit Write.
u32	CMD_READWRITELARGE
	Address Offset: 0x54 - 32-bit Read/Write.
u32	CMD_READLARGE
	Address Offset: 0x58 - 32-bit Read.

Detailed Description

SPI hardware register map.

Note: This is the main structure that maps directly onto the SPI peripheral memory-mapped register layout.

Definition at line 173 of file spi.h.

Field Documentation

◆ CLOCKDIVIDER

u32 spi_hwreg_t::CLOCKDIVIDER

Address Offset: 0x20 - Clock Divider.

Definition at line 179 of file spi.h.

◆ CMD

u32 spi_hwreg_t::CMD

Address Offset: 0x00 - Command Register.

Definition at line 174 of file spi.h.

◆ CMD_READLARGE

u32 spi_hwreg_t::CMD_READLARGE

Address Offset: 0x58 - 32-bit Read.

Definition at line 187 of file spi.h.

◆ CMD_READWRITELARGE

u32 spi_hwreg_t::CMD_READWRITELARGE

Address Offset: 0x54 - 32-bit Read/Write.

Definition at line 186 of file spi.h.

◆ CMD_WRITELARGE

u32 spi_hwreg_t::CMD_WRITELARGE

Address Offset: 0x50 - 32-bit Write.

Definition at line 185 of file spi.h.

◆ CONFIG

u32 spi_hwreg_t::CONFIG

Address Offset: 0x08 - Configuration Register.

Definition at line 176 of file spi.h.

◆ INTERRUPT

u32 spi_hwreg_t::INTERRUPT

Address Offset: 0x0C - Interrupt Control.

Definition at line 177 of file spi.h.

◆ RESERVED0

u32 spi_hwreg_t::RESERVED0[4]

Reserved.

Definition at line 178 of file spi.h.

◆ RESERVED1

u32 spi_hwreg_t::RESERVED1[7]

Reserved.

Definition at line 184 of file spi.h.

◆ RSP

u32 spi_hwreg_t::RSP

Address Offset: 0x04 - Response Register.

Definition at line 175 of file spi.h.

◆ SSACTIVEHIGH

u32 spi_hwreg_t::SSACTIVEHIGH

Address Offset: 0x30 - SS Polarity.

Definition at line 183 of file spi.h.

◆ SSDISABLE

u32 spi_hwreg_t::SSDISABLE

Address Offset: 0x2C - SS Disable Cycles.

Definition at line 182 of file spi.h.

◆ SSHOLD

u32 spi_hwreg_t::SSHOLD

Address Offset: 0x28 - SS Hold Cycles.

Definition at line 181 of file spi.h.

◆ SSSETUP

u32 spi_hwreg_t::SSSETUP

Address Offset: 0x24 - SS Setup Cycles.

Definition at line 180 of file spi.h.

The documentation for this struct was generated from the following file:

C:/Users/JasonLau/Downloads/workspace_local/GitLab/efx_IP/efx_soc_rv64/embedded_sw/software/standalone/driver/spi/spi.h

Data Fields