Register bitmasks and offsets.
SPI_CMD Register Bits | |
Offset: 0x00 | |
| #define | SPI_CMD_DATA_MASK 0xFF |
| Mask for Data to be transmitted. | |
| #define | SPI_CMD_WR (1 << 8) |
| Write Trigger. | |
| #define | SPI_CMD_RD (1 << 9) |
| Read Trigger. | |
| #define | SPI_CMD_SS (1 << 11) |
| Slave Select Trigger. | |
| #define | SPI_CMD_READ_INVALID (1 << 31) |
| Read Data Invalid Flag. | |
SPI_RSP Register Bits | |
Offset: 0x04 | |
| #define | SPI_RSP_CMD_FIFO_AVAILABILITY (0xFFFF) |
| Mask for CMD FIFO count. | |
| #define | SPI_RSP_FIFO_OCCUPANCY (0xFFFF << 16) |
| Mask for RSP FIFO count. | |
SPI_CONFIG Register Bits | |
Offset: 0x08 | |
| #define | SPI_CONFIG_CPOL (1 << 0) |
| Clock Pola. | |
| #define | SPI_CONFIG_MODE (1 << 4) |
| Line Mode (Dual/Q. | |
| #define | SPI_CONFIG_CPHA (1 << 16) |
| Clock P. | |
SPI_INTERRUPT Register Bits | |
Offset: 0x0C | |
| #define | SPI_INTC_CMD_INT_ENABLE (1 << 0) |
| Command FIFO Empty Interrupt En. | |
| #define | SPI_INTC_RSP_INT_ENABLE (1 << 1) |
| Response FIFO Valid Interrupt En. | |
| #define | SPI_CMD_INT (1 << 8) |
| Command Interrupt St. | |
| #define | SPI_RSP_INT (1 << 9) |
| Response Interrupt St. | |
| #define | SPI_CMD_VALID (1 << 16) |
| Command Valid S. | |
| #define SPI_CMD_DATA_MASK 0xFF |
| #define SPI_CMD_INT (1 << 8) |
| #define SPI_CMD_READ_INVALID (1 << 31) |
| #define SPI_CMD_SS (1 << 11) |
| #define SPI_CMD_VALID (1 << 16) |
| #define SPI_CONFIG_MODE (1 << 4) |
| #define SPI_INTC_CMD_INT_ENABLE (1 << 0) |
| #define SPI_INTC_RSP_INT_ENABLE (1 << 1) |
| #define SPI_RSP_CMD_FIFO_AVAILABILITY (0xFFFF) |
| #define SPI_RSP_FIFO_OCCUPANCY (0xFFFF << 16) |