riscv.h File Reference

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Overview

RISC-V related functions and definitions.

Author

Efinix Inc

Copyright

2013-2026 Efinix Inc. All rights reserved.
See the full License Information for Efinix and SaxonSoc MIT terms.

Definition in file riscv.h.

Macros
#define	csr_swap(csr, val)
	This function is used to swap the value of a CSR with a specified value.
#define	csr_read(csr)
	This function is used to read the value of a CSR.
#define	csr_write(csr, val)
	This function is used to write a value to a CSR.
#define	csr_read_set(csr, val)
	This function is used to read and set a CSR with a specified value.
#define	csr_set(csr, val)
	This function is used to set a CSR to a specified value.
#define	csr_read_clear(csr, val)
	This function is used for performing a read-clear operation on the specified CSR.
#define	csr_clear(csr, val)
	This function is used to clear a CSR.
#define	opcode_R(opcode, func3, func7, rs1, rs2)
	Macor for generating the opcode of an R-type instruction.
#define	cfu_type_R(func3, func7, rs1, rs2)
	Macros for defining custom R-type instructions with specific opcodes and function fields.
#define	cfu_push(func3, func7, rs1, rs2)
	Macros for defining cfu_push and cfu_pop instructions using the CUSTOM1 opcode.
#define	cfu_pop2()
#define	cfu_pop()
RISC-V M-Cause Interrupt Register Bitmasks
#define	CAUSE_SUPERVISOR_SOFTWARE   1
	Interrupt: Supervisor Software.
#define	CAUSE_MACHINE_SOFTWARE   3
	Interrupt: Machine Software.
#define	CAUSE_USER_TIME   4
	Interrupt: User Timer.
#define	CAUSE_SUPERVISOR_TIMER   5
	Interrupt: Supervisor Timer.
#define	CAUSE_MACHINE_TIMER   7
	Interrupt: Machine Timer.
#define	CAUSE_USER_EXTERNAL   8
	Interrupt: User External.
#define	CAUSE_SCALL   9
	Interrupt: Supervisor Call.
#define	CAUSE_MACHINE_EXTERNAL   11
	Interrupt: Machine External.
RISC-V M-Cause Exception Register Bitmasks
#define	CAUSE_INSTRUCTION_ADDR_MISALIGNED   0
	Exception: Instruction Address Misaligned.
#define	CAUSE_ACCESS_FAULT   1
	Exception: Instruction Access Fault.
#define	CAUSE_ILLEGAL_INSTRUCTION   2
	Exception: Illegal Instruction.
#define	CAUSE_BREAKPOINT   3
	Exception: Breakpoint.
#define	CAUSE_LOAD_ADDR_MISALIGNED   4
	Exception: Load Address Misaligned.
#define	CAUSE_LOAD_ACCESS_FAULT   5
	Exception: Load Access Fault.
#define	CAUSE_STORE_AMO_ADDR_MISALIGNED   6
	Exception: Store/AMO Address Misaligned.
#define	CAUSE_STORE_AMO_ACCESS_FAULT   7
	Exception: Store/AMO Access Fault.
#define	CAUSE_ENV_CALL_U_MODE   8
	Exception: Environment Call from U Mode.
#define	CAUSE_ENV_CALL_S_MODE   9
	Exception: Environment Call from S Mode.
#define	CAUSE_ENV_CALL_M_MODE   11
	Exception: Environment Call from M Mode.
#define	CAUSE_INSTRUCTION_PAGE_FAULT   12
	Exception: Instruction Page Fault.
#define	CAUSE_LOAD_PAGE_FAULT   13
	Exception: Load Page Fault.
#define	CAUSE_STORE_AMO_PAGE_FAULT   15
	Exception: Store/AMO Page Fault.
RISC-V MEDELEG and MIDELEG Register Bitmasks
#define	MEDELEG_INSTRUCTION_PAGE_FAULT   (1 << 12)
	Delegate Instruction Page Fault to S-mode.
#define	MEDELEG_LOAD_PAGE_FAULT   (1 << 13)
	Delegate Load Page Fault to S-mode.
#define	MEDELEG_STORE_PAGE_FAULT   (1 << 15)
	Delegate Store/AMO Page Fault to S-mode.
#define	MEDELEG_USER_ENVIRONNEMENT_CALL   (1 << 8)
	Delegate Environment Call from U-mode to S-mode.
#define	MIDELEG_SUPERVISOR_SOFTWARE   (1 << 1)
	Delegate Supervisor Software Interrupt to S-mode.
#define	MIDELEG_SUPERVISOR_TIMER   (1 << 5)
	Delegate Supervisor Timer Interrupt to S-mode.
#define	MIDELEG_SUPERVISOR_EXTERNAL   (1 << 9)
	Delegate Supervisor External Interrupt to S-mode.
RISC-V External Interrupt (PLIC) Bitmasks
#define	MIE_MSIE   (1 << CAUSE_MACHINE_SOFTWARE)
	Machine Software Interrupt Enable (Bit 3).
#define	MIE_MTIE   (1 << CAUSE_MACHINE_TIMER)
	Machine Timer Interrupt Enable (Bit 7).
#define	MIE_MEIE   (1 << CAUSE_MACHINE_EXTERNAL)
	Machine External Interrupt Enable (Bit 11).
RISC-V Time Related Register (Read-Only)
#define	RDCYCLE   0xC00
	Read-only cycle Cycle counter for RDCYCLE instruction.
#define	RDTIME   0xC01
	Read-only time Timer for RDTIME instruction.
#define	RDINSTRET   0xC02
	Read-only instret Instructions-retired counter for RDINSTRET instruction.
#define	RDCYCLEH   0xC80
	Read-only cycleh Upper 32 bits of cycle, RV32I only.
#define	RDTIMEH   0xC81
	Read-only timeh Upper 32 bits of time, RV32I only.
#define	RDINSTRETH   0xC82
	Read-only instreth Upper 32 bits of instret, RV32I only.