Revision History
| Date | Document Version | IP Version | Description |
|---|---|---|---|
| July 2025 | 3.0 | 5.14 | Corrected on Interrupt Status Register in Control Status Registers
R/W access attribute table. (DOC-2609) Added more details on the
Video Timing Parameter Definition table in the Video Timing
Parameters topic. Corrected the frame_num port description
in Video Interface table. (DOC-2605) |
| May 2025 | 2.9 | 5.12 | Updated example design. (SIP-891) Example Design IO bank update
(HVIO 3.3V). (SIP-907) Updated Customizing the MIPI 2.5G CSI-2 TX Controller. Updated observation after
downloading bitstream and Example Design Implementation table in
Example Design. Added description on debug port for
ready_to_xmit and init_skewcal_done in table Debug
Interface. Updated figure Reset Sequence and
Initialization to include hard D-Phy requirements.
(SIP-938) Updated Reset Sequence and Initialization topic.
(DOC-2485) |
| March 2025 | 2.8 | 5.11 | Updated Resource Utilization and Performance section.
(SIP-867) Updated Interleaved Data Transmission Waveform
(Per-Frame) and Interleaved Data Transmission Waveform
(Per-Horizontal Line). (DOC-2442) |
| January 2025 | 2.7 | 5.11 | Example design update to add Reset Seq and Init Session delay.
(SIP-805) Updated Figure Video Timing Waveform (Vertical),
Interleaved Data Transmission Waveform (Per-Frame), and Interleaved
Data Transmission Waveform (Per-Horizontal Line).
(SIP-823) Added note in Table: Video Interface in Ports
topic for user to fully utilize the pixel data bus.
(SIP-819) Added description for DPHY Clock Mode and Enable
Extra Bit on Virtual Channel in Table 1. (DOC-2307) Example design update to align with MIPI
Utility change (DOC-1783). (SIP-792) |
| December 2024 | 2.6 | 5.10 | Added debug ports for internal signal observation and monitoring in
Ports and Customizing the MIPI 2.5G CSI-2 TX Controller.
(SIP-580) Revised CSR address 0x10 usage in Control Status
Registers. (SIP-780) Added section Interleaved Data
Transmission with Virtual Channels. (SIP-784) |
| November 2024 | 2.5 | 5.9 | Added Topaz in Features and Device Support. (DOC-2102) Added IP
Version in Revision History. (DOC-2185) Added note for
Enable Skew Calibration in the MIPI 2.5G CSI-2 TX Controller Core
Parameter table. Disable skew cal for <1.5Gbps
operation. (SIP-523) |
| September 2024 | 2.4 | – | Updated Table 3. (DOC-2109) |
| September 2024 | 2.3 | – | Updated Reset Sequence and Initialization topic and Figure 1. (DOC-2048) Updated Features and tINIT_NS in Table 1. Added G400 in Table 1. Updated pixel data[63:0] in Figure 1. Removed data type RGB666 from Table 1. (DOC-2068) |
| July 2024 | 2.2 | – | Fixed typo in Table 3. (DOC-2004) |
| June 2024 | 2.1 | – | Updated Pixel FIFO depth requirement in table MIPI2.5G CSI-2 TX
Controller Core Parameter. (SIP-570) Added Reset Sequence and
Initialization sub-section. Corrected clk_esc frequency
from 100 Hz to 20MHz at table Clock and Reset Ports.
(DOC-1946) Added important note in Example Design and
Testbench regarding using default parameters options only.
(DOC-1781) |
| March 2024 | 2.0 | – | Updated content and topic title Minimum Horizontal Blanking Per Line to Minimum Horizontal Blanking Per Line Requirement. |
| October 2023 | 1.9 | – |
Updated MIPI video data format tables to include RGB information.
(DOC-1474)
Added more description for Enable Skew Calibration parameter.
(DOC-1453)
|
| September 2023 | 1.8 | – | Updated Minimum Horizontal Blanking Per Line formula and
example. Corrected supported HS data width.
(DOC-1437) |
| August 2023 | 1.7 | – | Updated Video Timing Waveform (Horizontal) figure and added Minimum Horizontal Blanking Per Line section. (DOC-1414) |
| July 2023 | 1.6 | – | Added more description for Accurate and Generic image frame modes. (DOC-1343) |
| June 2023 | 1.5 | – |
Corrected hsync_vcx and vsync_vcx signal directions.
(DOC-1341)
Added Device Support and release notes sections. (DOC-1234)
Updated supported data rate. (DOC-1217)
Updated port descriptions.
Added RAW16, RAW20, RAW24, and RAW28 format support.
Updated IP Core Frequency, Pixel Data FIFO Depth Size, Pack Type40,
Pack Type48, Pack Type56, Pack Type64 parameters.
Improved Interrupt Enable Register Definition descriptions.
Editorial changes.
|
| February 2023 | 1.4 | – | Added note about the resource and performance values in the resource and utilization table are for guidance only. |
| December 2022 | 1.3 | – | Updated PHY-Protocol Interface descriptions by indicating the clock
domains. (DOC-1022) Added New in Version section. |
| November 2022 | 1.2 | – | Corrected pixel clock calculation formula. (DOC-975) |
| August 2022 | 1.1 | – | Updated parameters for IP Manager support in Efinity software v2022.1. |
| August 2022 | 1.0 | – | Initial release. |