Customizing the MIPI 2.5G CSI-2 TX Controller

The core has parameters so you can customize its function. You set the parameters in the General tab of the core's IP Configuration window.

Table 1. MIPI 2.5G CSI-2 TX Controller Core Parameter
Name Options Description
Data Lanes 1, 2, 4 Number of data lanes.
Default: 4
MIPI Parallel Clock Frequency (MHz) 5 - 156 MIPI parallel clock (clk_byte_HS) frequency in MHz to support data rate of 80 Mbps to 2500 Mbps.
Default: 156
DPHY Clock Mode Continuous, Discontinuous Select HS clock mode.
Continuous refers to the HS byte clock continuously running during LP or HS mode.
Discontinuous refers to the HS byte clock in stopped condition during LP mode and in running condition during HS mode.
Default: Continuous
Pixel Data FIFO Depth Size 256 - 8192 FIFO depth size that stores the pixel packet data (set to power of 2 value).
Minimum FIFO depth required > horizontal_pixel (HACT) x bits_per_pixel / 64
Default: 1024
Image Frame Mode GENERIC, ACCURATE Selects image frame mode.
Generic mode: Frame format without accurate synchronization timing via Line Start and Line End.
Accurate mode: Frame format with accurate synchronization timing via Line Start and Line End.
Default: Generic
Enable Extra Bit on Virtual Channel Enable, Disable Enable - 16 virtual channels are available.
Disable - only 4 virtual channels are available.
Default: Disable
tINIT_NS Values according to MIPI D-PHY specifications. PHY initialization period in ns. Value must be 400000 or more.
Default: 400000
Initial tSKEWCAL (ns) Values according to MIPI D-PHY specifications. Initial skew calibration period in ns. Value must be 100000 or less.
Default: 100000
Number of Asynchronous Register Stages 2 – 8 Cross clock domain control signal synchronization stage.
Default: 2
Pack Type 40 Enable, Disable Enables the controller to pack RAW10, RAW20 YUV_420_10, and YUV_422_10 data type.1
Default: Enable
Pack Type 48 Enable, Disable Enables the controller to pack RAW6, RAW12, RAW24, RGB888, and YUV_420_8_legacy data type.1
Default: Enable
Pack Type 56 Enable, Disable Enables the controller to pack RAW7, RAW14, and RAW28.1
Default: Enable
Pack Type 64 Enable, Disable Enables the controller to pack RAW8, RAW16, RGB444, RGB565, RGB555, YUV_422_8, YUV_420_8, generic long packet, user define 8-bit, and embedded 8-bit non image packet.1
Default: Enable
Enable Skew Calibration Enable, Disable Enables automatic skew calibration.
When enabled, there should not be any data transmission prior to the expiry of initial tSKEWCAL timing (after de-assertion of reset).
Default: Enable
Note: Skew calibration can be enabled or disabled during initialization phase. However, this is only applicable to data rate above 1.5 Gbps. Set it to Disable for data rate 1.5 Gbps and below.
PPI Interface Data Width 16 HS mode data width.
Default: 16
MIPI_CSI2_TX_DEBUG Enable, Disable Enables debug ports for internal signal observation and monitoring.
Default: Disable
1 Only enable the pack type that you are using to save logic resources.