Minimum Horizontal Blanking Per Line Requirement

Video data is typically clocked at 1-pixel data per 1-pixel clock. The MIPI 2.5G CSI-2 TX Controller Core includes a highly compressed 64-bit pixel data bus that offers the flexibility to clock multiple pixel data per 1-pixel clock depending on the data format (See Table 1). This compression introduces some latencies for the internal logic to decompress the pixel data, converting them into byte clock domain, and transmitting out as byte data into MIPI I/O. As a result, minimum horizontal blanking per line must be fulfilled to prevent any data corruption during pixel data transmission.

The minimum horizontal blanking per line (in pixel clock) is defined as:


HFP+HBP+HSA > `byte_data_transfer_period` - `pixel_data_valid_period` + `LP-HS_timing` Where, `byte_data_transfer_period` = (HACT * `bit_per_pixel`) / 16 / `Lane_NUM` * `byte_clk_period` `pixel_data_valid_period` = HACT / `pixels_per_clk` * `pixel_clk_period` `LP-HS_timing` = DPHY timing between the lower-power and high-speed mode transition. For more details, download the Titanium MIPI Utility.xlsm from the Support Center.