Ports

Table 1. Clock and Reset Ports
Port	Direction	Description
clk_esc	Input	IP core clock consumed by controller logics. 20MHz.
reset_esc_n	Input	IP core reset signal.
clk_byte_HS	Input	MIPI TX parallel clock This is a HS mode transmission clock.
reset_byte_HS_n	Input	MIPI TX parallel clock reset signal.
clk_pixel	Input	Pixel clock.
reset_pixel_n	Input	Pixel clock reset signal.
axi_clk	Input	AXI4-Lite interface clock.
axi_reset_n	Input	AXI4-Lite interface reset.

Note: Refer to the Interfaces User Guide in the Support Center for serial or parallel clock requirements.

Table 2. PHY-Protocol Interface
Port	Direction	Description
TxUlpsClk	Output	Transmit ULPS on Clock Lane. This signal is clocked with clk_esc and reset_esc_n. This active-high signal is asserted to cause a Clock lane module to enter the ULPS.
TxUlpsExitClk	Output	Transmit ULPS Exit Sequence. This signal is clocked with clk_esc and reset_esc_n. This active-high signal is asserted when ULPS is active and the protocol is ready to leave ULPS.
TxUlpsActiveClkNot	Input	ULPS (not) Active. This signal is clocked with clk_esc and reset_esc_n. This active-low signal is asserted to indicate that the lane is in ULPS.
TxUlpsEsc [NUM_DATA_LANE-1:0]	Output	Escape Mode Transmit ULPS. This signal is clocked with clk_esc and reset_esc_n. This active-high signal is asserted with TxRequestEsc to cause the lane module to enter the ULPS.
TxUlpsExit [NUM_DATA_LANE-1:0]	Output	Transmit ULPS Exit Sequence. This signal is clocked with clk_esc and reset_esc_n. This active-high signal is asserted when ULPS is active and the protocol is ready to leave ULPS.
TxRequestEsc [NUM_DATA_LANE-1:0]	Output	Escape Mode Transmit Request. This signal is clocked with clk_esc and reset_esc_n. This active-high signal is used to request escape sequences.
TxSkewCalHS [NUM_DATA_LANE-1:0]	Output	HS Transmit Skew Calibration. This bus is clocked with clk_byte_HS and reset_byte_HS_n. This is an optional signal to initiate the periodic deskew burst at the transmitter. A low-to-high transition causes the PHY to initiate the transmission of a skew calibration pattern. A high-to-low transition causes the PHY to end the transmission of a skew calibration pattern, and initiate an end-of-transmission sequence.
TxStopStateD [NUM_DATA_LANE-1:0]	Input	Data lane in Stop State. This is nn asynchronous active-high signal from the MIPI hard D-PHY to indicate that the data lane is in stop state.
TxStopStateC	Input	Clock lane in Stop State. This is an asynchronous active-high signal from the MIPI hard D-PHY to indicate that the clock lane is in stop state.
TxUlpsActiveNot [NUM_DATA_LANE-1:0]	Input	ULPS (not) Active. This signal is clocked with clk_esc and reset_esc_n. This active-low signal is asserted to indicate that the lane is in ULPS.
TxReadyHS [NUM_DATA_LANE-1:0]	Input	HS Transmit Ready. This bus is clocked with clk_byte_HS and reset_byte_HS_n. This active-high signal indicates that TxDataHS is accepted by the lane module to be serially transmitted.
TxRequestHS [NUM_DATA_LANE-1:0]	Output	HS Transmit Request and Data Valid. This bus is clocked with clk_byte_HS and reset_byte_HS_n. A low-to-high transition causes the lane module to initiate a start-of-transmission sequence. A high-to-low transition causes the lane module to initiate an end-of-transmission sequence. This active-high signal also indicates that the protocol is driving valid data on TxDataHS to be transmitted.
TxRequestHSc	Output	HS Transmit Request and Data Valid. This bus is clocked with clk_byte_HS and reset_byte_HS_n. A low-to-high transition causes the lane module to initiate a start-of-transmission sequence. A high-to-low transition causes the lane module to initiate an end-of-transmission sequence. This active-high signal causes the lane module to begin transmitting a HS clock.
TxDataHSn [HS_DATA_WIDTH-1:0]	Output	HS data to be transmitted for lane. This bus is clocked with clk_byte_HS and reset_byte_HS_n. n = lane 0 to 3
TxReqValidHSn [1:0]	Output	High-Speed Transmit Word Data Valid. This bus is clocked with clk_byte_HS and reset_byte_HS_n. When the High-Speed Transmit Data width is greater than 8 bits, it is necessary to indicate which 8-bit segments contain valid transmit data to be able to transmit any number of words. n = lane 0 to 3

Table 3. Video InterfaceAll signals are clocked with clk_pixel and reset_pixel_n.
Port	Direction	Description
hsync_vcx	Input	Active-high horizontal sync for virtual channel. x = virtual lane 0 to 15
vsync_vcx	Input	Active-high vertical sync for virtual channel. x = virtual lane 0 to 15
datatype [5:0]	Input	Data type of the long packet. Sampled at Hsync rising edge.
pixel_data [63:0]	Input	Video Data. The actual width is dependent on pixel type. Refer to the pixel encoding table.
pixel_data_valid	Input	Active-high pixel data enable. Once the TX VALID signal goes high, the MIPI TX interface expects to receive pixel data every clock cycle until the entire line is sent. Additionally, the TX VALID signal must remain high for the entire line.
haddr [15:0]	Input	16 bit horizontal number of pixels. Sampled at Hsync rising edge. Note: Total pixel count should be aligned to pixels-per-clock boundary to prevent ambiguity on the pixel_data[63:0].
line_num[15:0]	Input	Line number to use. Sampled at Hsync rising edge.
frame_num[15:0]	Input	Frame number to use. Sampled at Vsync rising edge.

Table 4. AXI4-Lite Interface
Interface to access Table 1.

All signals are clocked with axi_clk and axi_reset_n.
Port	Direction	Description
axi_awaddr [15:0]	Input	AXI4-Lite write address bus.
axi_awvalid	Input	AXI4-Lite write address valid strobe.
axi_awready	Output	AXI4-Lite write address ready signal.
axi_wdata [31:0]	Input	AXI4-Lite write data.
axi_wvalid	Input	AXI4-Lite write data valid strobe.
axi_wready	Output	AXI4-Lite write ready signal.
axi_bvalid	Output	AXI4-Lite write response valid strobe.
axi_bready	Input	AXI4-Lite write response ready signal.
axi_araddr [15:0]	Input	AXI4-Lite read address bus.
axi_arvalid	Input	AXI4-Lite read address valid strobe.
axi_arready	Output	AXI4-Lite read address ready signal.
axi_rdata [31:0]	Output	AXI4-Lite read data.
axi_rvalid	Output	AXI4-Lite read data valid strobe.
axi_rready	Input	AXI4-Lite read data ready signal.

Table 5. Debug InterfaceAll signals are clocked with axi_clk and axi_reset_n.
Port	Direction	Description
mipi_debug_out[31:0]	Output	Debug port. Present if the parameter MIPI_CSI2_TX_DEBUG is Enabled. The following is the list of internal signals that can be monitored. [0] = fifo_full [1] = fifo_empty [2] = non_support_longpkt [3] = ready_to_xmit (indicator for initialization done, prior to skewcal) [4] = init_skewcal_done (indicator for skewcal process completion) [5] = TxStopState_0 [6] = TxStopState_1 [7] = TxStopState_2 [8] = TxStopState_3 [9] = TxStopState_4 [10] = TxStopState_5 [11] = TxStopState_6 [12] = TxStopState_7 [31:13] = reserved
mipi_debug_in[31:0]	Input	Debug ports. Present if the parameter MIPI_CSI2_TX_DEBUG is Enabled. Currently no function has been implemented. Tie all input bits to zero. [31:0] = reserved