Control Status Registers

Table 1. Control Status Registers
Word Address Offset Name R/W Width (bits)
0x00 Interrupt Status Register Bit[1:0],[3] - R
Bit[2] - R/W1C1
 4
0x04 Interrupt Enable Register R/W 5
0x08 D-PHY stop state status for lane 0 to lane 7 R 8
0x0C D-PHY Ultra Low-Power State (ULPS) status R 9
0x10 D-PHY Skew Calibration Control R/W 8
0x14 Reserved – –
0x18 D-PHY ULPS control signal R/W 9
Table 2. Interrupt Status Register Definition (0x00)
Bit Name Description
0 Pixel FIFO full Pixel FIFO in the pixel-to-byte converter module is full.
1 Pixel FIFO empty Pixel FIFO in the pixel-to-byte converter module is empty.
2 Unsupported video data type The TX controller received an unsupported video data type from the user through port datatype[5:0].
3 Initialization complete The core asserts this signal high when tInit timing parameter is met. TX controller is ready to send MIPI transaction.
Table 3. Interrupt Enable Register Definition (0x04)Each enabled interrupt status bit is aggregated to the irq output port as indicator. By default, all interrupt enable registers are set to 1'b0 (disabled).
Bit Name Description
0 Pixel FIFO full interrupt enable Enable interrupt generation for PixelFIFO full status bit.
1 Pixel FIFO empty full interrupt enable Enable interrupt generation for PixelFIFO empty status bit.
2 Unsupported video data type full interrupt enable Enable interrupt generation for Unsupportedvideo data type status bit.
3 Initialization complete full interrupt enable Enable interrupt generation for Initialization complete status bit.
Table 4. D-PHY Ultra Low-Power State (ULPS) Status (0x0C)
Bit Name Description
0 TxUlpsActiveClkNot ULPS (not) Active.
The core deasserts this signal low to indicate that the clock lane is in ULPS.
8:1 TxUlpsActiveNot_7 to TxUlpsActiveNot_0 ULPS (not) Active.
The core deasserts this signal low to indicate that the data lane is in ULPS.
Table 5. D-PHY Skew Calibration Control Register Definition (0x10)
Bit Name Description
7:0 TxSkewCalHS[7:0] High-Speed Transmit Skew Calibration.
When the register is set to 1, core asserts TxSkewCalHS signal high causes the PHY to initiate a de-skew calibration.
When the register is set to 0, core deasserts TxSkewCalHS signal low causes the PHY to stop deskew pattern transmission and initiate an end-of-transmission sequence.
This feature is only applicable to data rate above 1.5 Gbps. Do not apply for data rate of 1.5 Gbps and below.
Table 6. D-PHY ULPS Control Signal Register Definition (0x18)
Bit Name Description
0 TxUlpsClk Transmit ULPS on Clock Lane.
The core asserts this signal high to cause a clock lane module to enter the ULPS. The lane module remains in this mode until TxUlpsClk is de-asserted.
8:1 TxUlpsEsc[7:0] Escape Mode Transmit ULPS.
For LP implementations, the core asserts this and TxRequestEsc signals high to cause the lane module to enter the ULPS. The lane module remains in this mode until TxRequestEsc is de-asserted.
1 Read register. Write 1 to clear the register.