Functional Description

The MIPI 2.5G CSI-2 TX Controller consists of the following blocks:
  • Control Status Registers—Registers that user can configure in runtime and statuses that user can read using the AXI4-lite interface
  • ECC Generator—Error correction code generator block
  • CRC Generator—Cyclic redundancy check generator block
  • Packetizer—Converts pixel data to MIPI data format
  • Pixel-to-Byte Converter—Interprets the video data type and converts the pixel data to 64-bit data format
  • Pixel FIFO—Manages clock domain conversion for the data from pixel clock domain to MIPI byte clock domain
  • Video Interface Detector— Detects the video interface signals such as hsync, vsync and determine the start of a video horizontal line or video vertical line
The core has a video, AXI4-lite, MIPI D-PHY, and clock and reset interfaces.
Figure 1. MIPI 2.5G CSI-2 TX Controller System Block Diagram