Tz100 Fractional Output Divider
Tz100 FPGAs have a fractional output divider, i.e., you can use an output divider that has a fractional part and an integer part. The advantage of the fractional part is that you can potentially get the clock output signals closer to a desired frequency.
Important: You cannot use the fractional output
divider at the same time as the programmable duty cycle.
To use this feature you choose local feedback mode in the Interface Designer and specify
the fractional options. The PLL feeds CLKOUT1 back into the M counter,
which causes the fractional part to propagate to all of the clock output signals.
Important: When using
CLKOUT1 for fractional feedback, you
cannot use the output from CLKOUT1 as a clock source for your
design.