Tz100 MIPI Electrical Specifications and Timing

The MIPI D-PHY transmitter and receiver are compliant to the MIPI Alliance Specification for D-PHY Revision 1.1.

Table 1. High–Speed MIPI D–PHY Transmitter (TX) DC Specifications
Parameter Description Min Typ Max Unit
VCMTX High–speed transmit static common–mode voltage. 150 200 250 mV
|Δ VCMTX(1,0)| VCMTX mismatch when output is Differential–1 or Differential–0. – – 5 mV
|VOD| High–speed transmit differential voltage. 140 200 270 mV
|Δ VOD| VOD mismatch when output is Differential–1 or Differential–0. – – 14 mV
VOHHS High–speed output high voltage. – – 360 mV
ZOS Single ended output impedance. 40 50 60 Ω
Δ ZOS Single ended output impedance mismatch. – – 20 %
Table 2. High–Speed MIPI D–PHY Transmitter (TX) AC Specifications
Parameter Description Min Typ Max Unit
ΔVCMTX(HF) Common-level variations above 450 MHz. – – 15 mVRMS
ΔVCMTX(LF) Common-level variations between 50 to 450 MHz. – – 25 mVPEAK
tR and tF Rise and fall time < 1.0 Gbps. – – 0.3 UI
Rise and fall time > 1.0 Gbps. – – 0.35 UI
Rise and fall time > 1.5 Gbps. – – 0.4 UI
Table 3. Low–Power MIPI D–PHY Transmitter (TX) DC Specifications
Parameter Description Min Typ Max Unit
VOH Thevenin output high level. 0.95 1.2 1.3 V
VOL Thevenin output low level. –50 – 50 mV
ZOLP Output impedance of low–power transmitter. 110 – – Ω
Table 4. Low-Power MIPI D–PHY Transmitter (TX) AC Specifications
Parameter Description Min Typ Max Unit
TRLP/TFLP 15%-85% rise time and fall time. – – 25 ns
TREOT 30%-85% rise time and fall time. – – 35 ns
TLP-PULSE-TX Pulse width of first LP exclusive-OR clock pulse after Stop state or last pulse before Stop state. 40 – – ns
Pulse width of all other pulses. – 20 – ns
TLP-PER-TX Period of the LP exclusive-OR clock. 90 – – ns
δV/δtSR Slew rate at CLOAD = 50 pF < 1.5 Gbps. 30 – 150 mV/ns
Slew rate at CLOAD = 50 pF > 1.5 Gbps. 25 – 150 mV/ns
Table 5. High–Speed MIPI D–PHY Receiver (RX) DC Specifications
Parameter Description Min Typ Max Unit
VCMRX(DC) Common mode voltage high–speed receive mode. 70 – 330 mV
ZID Differential input impedance. 80 100 120 Ω
Table 6. High–Speed MIPI D–PHY Receiver (RX) AC Specifications
Parameter Description Min Typ Max Unit
ΔVCMRX(HF) Common-point interference above 450 MHz. – – 50 mV
ΔVCMRX(LF) Common-point interference between 50 MHz to 450 MHz. – – 25 mV
VIDTH Differential input high threshold. – – 40 mV
VIDTL Differential input low threshold. –40 – – mV
VIHHS Single–ended input high voltage. – – 460 mV
VILHS Single–ended input low voltage. –40 – – mV
VTERM–EN Single–ended threshold for high–speed termination enable. – – 450 mV
CCP Common-point termination. – – 60 pF
Table 7. Low–Power MIPI D–PHY Receiver (RX) DC Specifications
Parameter Description Min Typ Max Unit
VIH Logic 1 input voltage. 740 – – mV
VIL Logic 0 input voltage, not in ULP state. – – 550 mV
VIL–ULPS Logic 0 input voltage, ULP state. – – 300 mV
VHYST Input hysteresis. 25 – – mV
Table 8. Low-Power MIPI D–PHY Receiver (RX) AC Specifications
Parameter Description Min Typ Max Unit
TMIN-RX Minimum pulse width response. 20 – – ns
VINT Peak interference amplitude. – – 200 mV
fINT Interference frequency. 450 – – MHz

Tz100 MIPI Reset Timing

The MIPI RX and TX interfaces have two reset signals (RESET and RST0_N) to reset the D-PHY controller logic. These signals are active low, and you should use them together to reset the MIPI interface.

The following waveform illustrates the minimum time required to reset the MIPI interface.

Figure 1. RESET and RST0_N Timing Diagram
Table 9. MIPI Timing
Symbol Parameter Min Typ Max Units
tINIT_A Minimum time between the rising edge of RESET and the start of MIPI RX or TX data. 350 – – μs
tINIT_D Minimum time between the rising edge of RST0_N and the start of MIPI RX or TX data. 1 – – clk