Tz100 DDR DRAM Interface

Important: All information is preliminary and pending definition.

The DDR PHY interface supports LPDDR4 memories with x32 DQ widths and a memory controller hard IP block. The memory controller provides two full-duplex AXI4 buses to communicate with the FPGA core.

Note: The DDR PHY and controller are hard blocks; you cannot bypass the DDR DRAM memory controller to access the PHY directly for non-DDR memory controller applications.

Figure 1. DDR DRAM Block Diagram

Figure 2. DDR DRAM Interface Block Diagram
Note: The PLL reference clock must be driven by I/O pads. The Efinity software issues a warning if you do not connect the reference clock to an I/O pad. (Using the clock tree may induce additional jitter and degrade the DDR performance.)
Additionally, the PLL that clocks the DDR DRAM interface should not use programmable duty cycle, fractional output, or spread-spectrum clocking because these features increase jitter.
Refer to PLL for more information about the PLL block.
Table 1. DDR DRAM Pads
Signal Direction Description
DDR_A[5:0] Output Address signals to the DRAM.
DDR_CS_N[3:0] Output Chip select to the DRAM.
DDR_CKE[1:0] Output Active-high clock enable signals to the DRAM.
DDR_RST_N Output Active-low reset signal to the DRAM.
DDR_CK Output Differential clock signals to the DRAM.
DDR_CK_N Output
DDR_DQ[n:0] Bidirectional Data bus to/from the memories. For writes, the FPGA drives these signals. For reads, the memory drives these signals. These signals are connected to the DQ pins on the memories. n is 15 or 31 depending on the Data Width setting. If unused, can be left floating on the board.
DDR_DQS_N[m:0] Bidirectional Differential data strobes to/from the memories. For writes, the FPGA drives these signals. For reads, the memory drives these signals. These signals are connected to the DQS pins on the memories. m is 1or 3 depending on the DQ width. If unused, can be left floating on the board.
DDR_DQS[m:0] Bidirectional
DDR_DM[m:0] Bidirectional Signals used as active-high data-mask and data bus inversion indicator. m is 1 or 3 depending on the DQ width.
If data bus inversion is enabled for a write operation, the DDR controller will drive the signal high if the write data byte is inverted. Similarly, if data bus inversion is enabled for a read operation, the memory device will drive the signal high if the read data byte is inverted.
If unused, can be left floating on the board.
Table 2. Calibration Resistor Pad
Signal Direction Description
DDR_CAL Input Calibration resistor connection. Connect to the ground through a 240 Ω resistor on your board.
Table 3. Controller Status Signals
Signal Direction Clock Domain Description
CTRL_CLK Input N/A Clock for controller status signals.
CTRL_INT Output N/A Controller detects Interrupt.
CTRL_MEM_RST_VALID Output N/A Controller has been reset.
CTRL_REFRESH Output CTRL_CLK Indicate controller is executing refresh command.
CTRL_CKE[1:0] Output CTRL_CLK Delayed 'control_cke' from the controller, indicating that the memory is in self-refresh or power down mode.
CTRL_BUSY Output CTRL_CLK Controller is busy reading data.
CTRL_CMD_Q_ALMOST_FULL Output CTRL_CLK Command queue reached 'q_fullness' parameter.
CTRL_DP_IDLE Output CTRL_CLK Datapath is idle.
CTRL_PORT_BUSY[1:0] Output CTRL_CLK Indicate if port is reading data.
Table 4. Configuration Controller Signals
Signal Direction Description
CFG_RESET Input Active-high configuration controller reset. Asserting this signal also resets the DDR controller, PHY and the DRAM device.
CFG_START Input Start the configuration controller.
CFG_DONE Output Indicates the configuration controller is done
CFG_SEL Input Tie this input to low to enable the configuration controller.
Table 5. AXI4 Global Signals (Interface to FPGA Core Logic)
Signal Direction Clock Domain Description
ACLK_x Input N/A AXI4 clock inputs.
ARSTN_x Input ACLK_x Active-low reset signal to the AXI interface.
Table 6. AXI4 Write Response Channel Signals (Interface to FPGA Core Logic)
Signal
x is 0 or 1
 Direction Clock Domain Description
BID_x[5:0] Output ACLK_x Response ID tag. This signal is the ID tag of the write response.
BREADY_x Input ACLK_x Response ready. This signal indicates that the master can accept a write response.
BRESP_x[1:0] Output ACLK_x Read response. This signal indicates the status of the read transfer.
BVALID_x Output ACLK_x Write response valid. This signal indicates that the channel is signaling a valid write response.
Table 7. AXI4 Read Data Channel Signals (Interface to FPGA Core Logic)
Signal
x is 0 or 1
 Direction Clock Domain Description
RDATA_x[511:0] Output ACLK_x Read data.
RID_x[5:0] Output ACLK_x Read ID tag. This signal is the identification tag for the read data group of signals generated by the slave.
RLAST_x Output ACLK_x Read last. This signal indicates the last transfer in a read burst.
RREADY_x Input ACLK_x Read ready. This signal indicates that the master can accept the read data and response information.
RRESP_x[1:0] Output ACLK_x Read response. This signal indicates the status of the read transfer.
RVALID_x Output ACLK_x Read valid. This signal indicates that the channel is signaling the required read data.
Table 8. AXI4 Write Data Channel Signals (Interface to FPGA Core Logic)
Signal
x is 0 or 1
 Direction Clock Domain Description
WDATA_x[511:0] Input ACLK_x Write data.
WLAST_x Input ACLK_x Write last. This signal indicates the last transfer in a write burst.
WREADY_x Output ACLK_x Write ready. This signal indicates that the slave can accept the write data.
WSTRB_x[63:0] Input ACLK_x Write strobes. This signal indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus.
WVALID_x Input ACLK_x Write valid. This signal indicates that valid write data and strobes are available.
Table 9. AXI4 Read Address Signals (Interface to FPGA Core Logic)
Signal
x is 0 or 1
 Direction Clock Domain Description
ARADDR_x[32:0] Input ACLK_x Read address. It gives the address of the first transfer in a burst transaction.
ARBURST_x[1:0] Input ACLK_x Burst type. The burst type and the size determine how the address for each transfer within the burst is calculated.
’b01 = INCR
’b10 = WRAP
ARID_x[5:0] Input ACLK_x Address ID. This signal identifies the group of address signals.
ARLEN_x[7:0] Input ACLK_x Burst length. This signal indicates the number of transfers in a burst.
ARREADY_x Output ACLK_x Address ready. This signal indicates that the slave is ready to accept an address and associated control signals.
ARSIZE_x[2:0] Input ACLK_x Burst size. This signal indicates the size of each transfer in the burst.
ARVALID_x Input ACLK_x Address valid. This signal indicates that the channel is signaling valid address and control information.
ARLOCK_x Input ACLK_x Lock type. This signal provides additional information about the atomic characteristics of the transfer.
ARAPCMD_x Input ACLK_x Read auto-precharge.
ARQOS_x Input ACLK_x QoS identifier for read transaction.
Table 10. AXI4 Write Address Signals (Interface to FPGA Core Logic)
Signal
x is 0 or 1
 Direction Clock Domain Description
AWADDR_x[32:0] Input ACLK_x Write address. It gives the address of the first transfer in a burst transaction.
AWBURST_x[1:0] Input ACLK_x Burst type. The burst type and the size determine how the address for each transfer within the burst is calculated.
AWID_x[5:0] Input ACLK_x Address ID. This signal identifies the group of address signals.
AWLEN_x[7:0] Input ACLK_x Burst length. This signal indicates the number of transfers in a burst.
AWREADY_x Output ACLK_x Address ready. This signal indicates that the slave is ready to accept an address and associated control signals.
AWSIZE_x[2:0] Input ACLK_x Burst size. This signal indicates the size of each transfer in the burst.
AWVALID_x Input ACLK_x Address valid. This signal indicates that the channel is signaling valid address and control information.
AWLOCK_x Input ACLK_x Lock type. This signal provides additional information about the atomic characteristics of the transfer.
AWAPCMD_x Input ACLK_x Write auto-precharge.
AWQOS_x Input ACLK_x QoS identifier for write transaction.
AWCACHE_x[3:0] Input ACLK_x Memory type. This signal indicates how transactions are required to progress through a system.
AWALLSTRB_x Input ACLK_x Write all strobes asserted. The DDR controller only supports a maximum of 16 AXI beats for write commands using this signal.
AWCOBUF_x Input ACLK_x Write coherent bufferable selection.
AWCACHE_x must be set to 'b1111 for
AWCOBUF_x when:
  • 'b0 = Bvalid Response is returned when both command and data have been received by the port.
  • 'b1 = Bvalid Response is returned when command is accepted into the controller command queue.
When AWCACHE_x is set to 'b0000:
  • Bvalid Response is returned when command is issued to PHY.

DDR DRAM Interface Input Clocks

You only need one clock to drive the DDR DRAM interface block. To select the PLL as the clock source for the DDR DRAM block, choose CLKIN 0, CLKIN 1, or CLKIN 2 as the Clock Source in the Interface Designer.

Table 11. Input Clocks
DDR Block PLL Resource PLL CLKOUT
CLKIN 0 CLKIN 1 CLKIN 2
DDR 0 BL0 BL1 BL2 CLKOUT3

CLKOUT3 of the selected PLL drives the DDR DRAM interface block. The clock runs at a quarter of the PHY data rate (for example, 2,000 Mbps requires a 500 MHz clock). You need to instantiate the selected PLL in the Interface Designer and configure the PLL's CLKOUT3 with the required frequency. The Efinity software then connects the PLL's CLKOUT3 signal to the DDR DRAM interface block automatically.