Efinix, Inc.
  • Tz100 Introduction
  • Tz100 Features
    • Tz100 Available Package Options
  • Tz100 Device Core Functional Description
    • Tz100 XLR Cell
    • Tz100 Embedded Memory
      • Tz100 True Dual-Port Mode
      • Tz100 Simple Dual-Port Mode
    • Tz100 DSP Block
    • Tz100 Clock and Control Network
      • Tz100 Clock Sources that Drive the Global and Regional Networks
      • Tz100 Driving the Global Network
      • Tz100 Driving the Regional Network
      • Tz100 Driving the Local Network
  • Tz100 Device Interface Functional Description
    • Tz100 Interface Block Connectivity
    • Tz100 GPIO
      • Tz100 Features for HVIO and HSIO Configured as GPIO
        • Tz100 Double-Data I/O
        • Tz100 Programmable Delay Chains
      • Tz100 HVIO
      • Tz100 HSIO
        • Tz100 HSIO Configured as GPIO
        • Tz100 HSIO Configured as LVDS
        • Tz100 HSIO Configured as MIPI Lane
      • Tz100 I/O Banks
    • Tz100 DDR DRAM Interface
    • Tz100 MIPI D-PHY
      • Tz100 MIPI RX D-PHY
      • Tz100 MIPI TX D-PHY
    • Tz100 Oscillator
    • Tz100 Fractional PLL
      • Tz100 Reference Clock Resource Assignments
      • Tz100 Programmable Duty Cycle
      • Tz100 Fractional Output Divider
      • Tz100 Spread-Spectrum Clocking
      • Tz100 Dynamic PLL Reconfiguration
      • Tz100 Dynamic Phase Shift
    • Tz100 Spread-Spectrum Clocking PLL
    • Tz100 Hardened RISC-V Block Interface
    • Tz100 Transceiver Interface
    • Tz100 Single-Event Upset Detection
    • Tz100 Internal Reconfiguration Block
  • Tz100 Security Feature
  • Tz100 Power Sequence
    • Tz100 Power-Up Sequence
    • Tz100 Power-Down Sequence
    • Tz100 Power Supply Current Transient
    • Tz100 Unused Resources and Features
  • Tz100 Configuration
    • Tz100 Supported Configuration Modes
  • Tz100 Characteristics and Timing
    • Tz100 DC and Switching Characteristics
    • Tz100 HSIO Electrical and Timing Specifications
    • Tz100 MIPI Electrical Specifications and Timing
      • Tz100 MIPI Reset Timing
    • Tz100 PLL Timing and AC Characteristics
    • Tz100 Configuration Timing
      • Tz100 JTAG Mode
      • Tz100 SPI Active Mode
      • Tz100 SPI Passive Mode
    • Tz100 Transceiver Specifications
  • Tz100 Pinout Description
    • Tz100 Configuration Pins
    • Tz100 Dedicated DDR Pinout
    • Tz100 Dedicated MIPI D-PHY Pinout
    • Tz100 Dedicated Transceiver Pinout
    • Tz100 Pin States
  • Tz100 Interface Floorplan
  • Tz100 Efinity Software Support
  • Tz100 Ordering Codes
  • Tz100 Revision History

Tz100 Characteristics and Timing

The following table shows the specification status for Tz100 packages.

Table 1. Package Status
Package Status
N441 Preliminary
N484 Preliminary
N576 Preliminary
N676 Preliminary
  • Tz100 DC and Switching Characteristics
  • Tz100 HSIO Electrical and Timing Specifications
  • Tz100 MIPI Electrical Specifications and Timing
  • Tz100 PLL Timing and AC Characteristics
  • Tz100 Configuration Timing
  • Tz100 Transceiver Specifications

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