Tz100 SPI Passive Mode

Figure 1. SPI Passive Mode (x1, Mode 3) Timing Sequence
Note:
  • The waveform shows the perspective from the control block without any optional external pull-up or pull-down resistors connected.
  • CDI input data is clocked by CCK. To prevent configuration failure, CCK must stop toggling if the bitstream data becomes invalid. You must resume with the next bitstream data before stopping to continue the configuration.
  • CSI must stay high during configuration.
  • SSL_N must stay low during configuration.
  • Efinix does not recommend connecting multiple slaves on the same SPI bus.
Important: To ensure successful configuration, the microprocessor must continue to supply the configuration clock to the Topaz™ FPGA for at least 100 cycles after sending the last configuration data.
Table 1. Passive Mode Timing
Symbol Parameter Min Typ Max Units
fMAX_S Passive mode configuration clock frequency. – – 100 MHz
tCLKH Configuration clock pulse width high. 4.8 – – ns
tCLKL Configuration clock pulse width low. 4.8 – – ns
tSU Setup time (x1, x2, x4, x8). 2 – – ns
Setup time (x16, x32). 6 – – ns
tH Hold time. 2 – – ns
tDMIN Minimum time between deassertion of CRESET_N to first valid configuration data. 32 – – μs
Important: The JTAG pins must be inactive during SPI passive configuration.
The EXT_CONFIG_CLK pin must be inactive during SPI passive configuration.