Tz100 Device Core Functional Description

Tz100 FPGAs feature an eXchangeable Logic and Routing (XLR) cell that Efinix® has optimized for a variety of applications. Topaz™ FPGAs contain LEs that are constructed from XLR cells. Each FPGA in the Topaz™ family has a custom number of building blocks to fit specific application needs. As shown in the following figure, the FPGA includes I/O ports on all four sides, as well as columns of LEs, memory, and DSP blocks. A control block within the FPGA handles configuration.

Figure 1. Tz100 FPGA Block Diagram
Interface blocks include GPIO, LVDS, PLL, MIPI lane I/O, MIPI D-PHY, DDR DRAM, RISC-V, and transceivers.