Features

  • High-density, low-power Quantum® compute fabric
  • Built on TSMC 16 nm process
  • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM
  • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting
  • Versatile on-chip clocking
    • Low-skew global network supporting 32 clock or control signals
    • Regional and local clock networks
    • PHY clock network and clock modifiers for high-speed clocking
    • Up to seven PLLs with support for fractional-N division, programmable duty cycle, spread-spectrum clocking, and dynamic reconfiguration
  • FPGA interface blocks
    • Three varieties of general-purpose I/O (GPIO) pins:
      • High-voltage I/O (HVIO) pins support 1.8, 2.5, and 3.3 V
      • Configurable high-speed I/O (HSIO) pins support
        • Single-ended and differential I/O
        • LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps
        • MIPI lane (DSI and CSI) in high-speed and low-power modes, up to 1.5 Gbps
      • Enhanced configurable high-speed I/O (HSIO2) support
        • Single-ended and differential I/O
        • LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.8 Gbps
        • MIPI lane (DSI and CSI) in high-speed and low-power modes, up to 2.5 Gbps
        • DDR3L up to 1,333 Mbps
    • One oscillator
  • Flexible device configuration
    • Standard SPI interface (active, passive, and daisy chain)
    • JTAG interface
    • Supports internal reconfiguration
  • Single-event upset (SEU) detection feature
  • Optional security feature
    • Asymmetric bitstream authentication using RSA-4096
    • Bitstream encryption/decryption using AES-GCM
  • Fully supported by the Efinity® software, an RTL-to-bitstream compiler
Important: All specifications are preliminary and pending hardware characterization.
Table 1. Ti95 FPGA Resources
Logic Elements (LEs) eXchangeable Logic and Routing (XLR) Cells Global Clock and Control Signals Embedded Memory (Mbits) Embedded Memory Blocks (10 Kbits) Embedded DSP Blocks
Total SRL81
93,200 83,066 14,573 Up to 32 4.5 450 210
Table 2. Ti95 Package-Dependent Resources
Resource F225 F324
Single-ended GPIO (maximum) HVIO
LVCMOS: 1.8, 2.5, 3.0, 3.3 V
LVTTL: 3.0, 3.3 V
 23 36
HSIO
LVCMOS, HSTL: 1.2, 1.5, 1.8 V
SSTL: 1.2, 1.35, 1.5, 1.8 V
 62 88
HSIO2
LVCMOS, HSTL: 1.2, 1.5, 1.8 V
SSTL: 1.2, 1.35, 1.5, 1.8 V
 78 110
Differential GPIO (maximum) HSIO (LVDS, Differential HSTL, SSTL, and MIPI TX Data and Clock Lanes) 31 44
HSIO2 (LVDS, Differential HSTL, SSTL, and MIPI TX Data and Clock Lanes) 39 55
HSIO (MIPI RX Data Lanes) 25 36
HSIO (MIPI RX Clock Lanes) 6 6
HSIO2 (MIPI RX Data Only Lanes) 23 55
HSIO2 (MIPI RX Data or Clock Lanes) 16 20
HSIO2 Byte Clock Groups 8 10
High-Speed DDR PHY Interface 2 x8 2 x16
Global clock or control signals from GPIO pins 24 32
Fractional PLLs 7 7
1 Number of XLR cells that can be configured as shift register with 8 maximum taps.