• Introduction
  • Features
    • Available Package Options
  • Ti95 Device Core Functional Description
    • Ti95 XLR Cell
    • Ti95 Embedded Memory
      • Ti95 True Dual-Port Mode
      • Ti95 Simple Dual-Port Mode
    • Ti95 DSP Block
    • Ti95 Clock and Control Network
      • Ti95 Clock Sources that Drive the Global and Regional Networks
      • Ti95 Driving the Global Network
      • Ti95 Driving the Regional Network
      • Ti95 Driving the Local Network
      • PHY Clock Network
      • Byte Clock Groups
  • Ti95 Device Interface Functional Description
    • Ti95 Interface Block Connectivity
    • Ti95 GPIO
      • Ti95 Features for HVIO, HSIO, and HSIO2 Configured as GPIO
        • Ti95 Double-Data I/O
        • Ti95 Programmable Delay Chains
      • Ti95 HVIO
      • Ti95 HSIO
        • Ti95 HSIO Configured as GPIO
        • Ti95 HSIO Configured as LVDS
        • Ti95 HSIO Configured as MIPI Lane
      • Ti95 HSIO2
        • Ti95 HSIO2 Configured as GPIO
        • Ti95 HSIO2 Configured as LVDS
        • Ti95 HSIO2 Configured as MIPI Lane
        • Ti95 HSIO2 Configured as QDRIO
      • I/O Banks
    • Ti95 Oscillator
    • Ti95 Fractional PLL
      • Ti95 Reference Clock Resource Assignments
      • Ti95 Programmable Duty Cycle
      • Ti95 Fractional Output Divider
      • Ti95 Spread-Spectrum Clocking
      • Ti95 Dynamic PLL Reconfiguration
      • Ti95 Dynamic Phase Shift
    • Ti95 Single-Event Upset Detection and Correction
    • Ti95 Internal Reconfiguration Block
  • Ti95 Security Feature
  • Ti95 Power Sequence
    • Ti95 Power-Up Sequence
    • Ti95 Power-Down Sequence
    • Ti95 Power Supply Current Transient
    • Ti95 Unused Resources and Features
  • Ti95 Configuration
    • Supported Configuration Modes
  • Ti95 Characteristics and Timing
    • Ti95 DC and Switching Characteristics
    • Ti95 HSIO and HSIO2 Electrical and Timing Specifications
    • Ti95 PLL Timing and AC Characteristics
    • Ti95 Configuration Timing
      • Ti95 JTAG Mode
      • Ti95 SPI Active Mode
      • Ti95 SPI Passive Mode
  • Ti95 Pinout Description
    • Ti95 Configuration Pins
    • Ti95 Pin States
  • Ti95 Interface Floorplan
  • Ti95 Efinity Software Support
  • Ti95 Ordering Codes
  • Revision History

Ti95 Power Sequence

Important: You must follow the power-up and power-down sequence when powering Titanium FPGAs.
  • Ti95 Power-Up Sequence
  • Ti95 Power-Down Sequence
  • Ti95 Power Supply Current Transient
  • Ti95 Unused Resources and Features