T13 SPI Flash Memory

The QFP100F3 packages include a T13 FPGA and a SPI flash memory. The SPI flash memory has a density of 16 Mbits and a clock rate of up to 20 MHz. In active configuration mode, the FPGA is configured using the configuration bitstream in the SPI flash memory. Typically you can fit two bitstream images into the QFP100F3 SPI flash. The SPI flash memory's VCC is powered by VCCIO1A_1B_1C.

In SPI active configuration mode, the FPGA is configured using a bitstream stored in the SPI flash device. During configuration, the maximum clock frequency for the flash device is specified in SPI Active. When the FPGA is in user mode, you can access the flash at the flash device's maximum clock frequency (although different SPI flash commands may have different maximum clock frequencies).

When a configuration bitstream is stored in the SPI flash and the SPI active hardware connection is properly established, the SPI active configuration can automatically start after the power-up. In QFP100F3 packages you are only required to connect the SS_N pin to the SPI_CS_N pin for the SPI active configuration to start automatically. This is additional to other required configuration pin settings depending on the configuration mode you select.

Notice: Refer to the AN 006: Configuring Trion FPGAs for detailed configuration requirements.

You can also use the SPI flash to store user data during user mode. To read or write the SPI flash during user mode, you must create the SPI flash interface block in the Efinity Interface Designer.

Notice: Refer to Trion Interfaces User Guide for more information about using the SPI flash interface block in the Efinity Interface Designer.

Important: You can only use the internal SPI flash in user mode if no LVDS TX is used.

Figure 1. Connections between FPGA and SPI Flash Device inside the Package

Table 1. SPI Flash Memory Signals (Interface to FPGA Fabric)
Signal	Direction	Description
SCLK	Input	Clock output to SPI flash memory.
MOSI	Input	Data output to SPI flash memory.
MISO	Output	Data input from SPI flash memory.
WP_N	Input	Active-low write protect signal.
HOLD_N	Input	Active-low hold signal.
SPI_CS_N	Input	Active-low SPI flash memory chip select.