T13 Embedded Memory
The core has 5-kbit high-speed, synchronous, embedded SRAM memory blocks. Memory blocks can operate as single-port RAM, simple dual-port RAM, true dual-port RAM, FIFOs, or ROM. You can initialize the memory content during configuration. The Efinity® software includes a memory cascading feature to connect multiple blocks automatically to form a larger array. This feature enables you to instantiate deeper or wider memory modules.
Note: The block RAM content is random and undefined if it is not
initialized.
The memory read and write ports have the following modes for addressing the memory (depth x width):
| 256 x 16 | 1024 x 4 | 4096 x 1 | 512 x 10 |
| 512 x 8 | 2048 x 2 | 256 x 20 | 1024 x 5 |
The read and write ports support independently configured data widths.
