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T13 Introduction
T13 Features
T13 Available Package Options
T13 Device Core Functional Description
T13 XLR Cell
T13 Logic Cell
T13 Embedded Memory
T13 Multipliers
T13 Global Clock Network
T13 Clock and Control Distribution Network
T13 Global Clock Location
T13 Device Interface Functional Description
T13 Interface Block Connectivity
T13 General-Purpose I/O Logic and Buffer
T13 Complex I/O Buffer
T13 Double-Data I/O
T13 I/O Banks
T13 PLL
T13 LVDS
T13 LVDS TX
T13 LVDS RX
T13 MIPI
T13 MIPI TX
T13 MIPI TX Video Data TYPE[5:0] Settings
T13 MIPI RX
T13 MIPI RX Video Data TYPE[5:0] Settings
T13 D-PHY Timing Parameters
T13 SPI Flash Memory
T13 Power Up Sequence
T13 Power Supply Current Transient
T13 Unused Resources and Features
T13 Configuration
T13 Supported Configuration Modes
T13 Mask-Programmable Memory Option
T13 DC and Switching Characteristics
T13 LVDS I/O Electrical and Timing Specifications
T13 ESD Performance
T13 MIPI Electrical Specifications and Timing
T13 MIPI Power-Up Timing
T13 MIPI Reset Timing
T13 PLL Timing and AC Characteristics
T13 Configuration Timing
T13 SPI Active
T13 SPI Passive
T13 JTAG
T13 Maximum tUSER for SPI Active and Passive Modes
T13 Pinout Description
T13 Pin States
T13 Efinity Software Support
T13 Interface Floorplan
T13 Ordering Codes
T13 Revision History
T13
ESD Performance
Refer to the
Trion Reliability Report
for ESD performance data.