Ports

Table 1. APB3 Ports

Name	Direction	Description
s_apb3_paddr[ADDR_WTH-1:0]	Input	APB3 address bus. It can be up to 32 bits wide and is driven by the APB3 master device. Write and read operations share the same address bus
s_apb3_psel	Input	APB3 master device generates this signal to each peripheral bus slave. This signal must always be high for write or read operations.
s_apb3_penable	Input	Enables the second and subsequent cycles of an APB3 transfers.
s_apb3_pwrite	Input	0: Read transfer 1: Write transfer
s_apb3_pwdata[31:0]	Input	APB3 write data bus.
s_apb3_pready	Output	Logic high indicates that the slave is ready to receive the next transfer.
s_apb3_prdata[31:0]	Output	APB3 read data bus.
s_apb3_pslverror	Output	Logic high indicates that there is no response from the AXI4 interface.

Table 2. AXI4-Lite Ports

Name	Direction	Description
m_axi_awready	Input	Indicates that the channel is signaling valid write address and control information.
m_axi_wready	Input	Indicates that the slave can accept the write data.
m_axi_arready	Input	Indicates that the slave is ready to accept an address and associated control signals.
m_axi_rdata[31:0]	Input	Content of the read data.
m_axi_rvalid	Input	Indicates that the channel is signaling valid read address and control information.
m_axi_awaddr[ADDR_WTH-1:0]	Output	Copy address of the APB3 on write transfer.
m_axi_awvalid	Output	Indicates that the valid read data is available.
m_axi_wdata[31:0]	Output	Data to be written.
m_axi_wvalid	Output	Indicates that the channel is signaling valid write address and control information.
m_axi_arraddr[ADDR_WTH-1:0]	Output	Copy address of the APB3 on read transfer.
m_axi_arvalid	Output	Indicates that a valid read data is available.
m_axi_rready	Output	Indicates that the channel is signaling the required read data. This signal is constantly high.

Table 3. Clock and Reset Ports

Name	Direction	Description
clk	Input	All signals are synchronous to this clock.
rstn	Input	Synchronous reset signal that initializes all internal pointers and output flags.