APB3 to AXI4 Lite Converter Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.
The example design targets the Trion® T20 BGA256 Development Board and Titanium Ti60 F225 Development Board. This design continuously performs write and read operations. The design then compares the data from each operation. The design displays the operation type and flags if it detects an error in the data or address of an operation through the board's LEDs.
  • Trion® T20 BGA256 Development Board—If there are no errors, the LEDs blink from LEDs D2, and D3 to LED D2 continuously.
  • Titanium Ti60 F225 Development Board—If there are no errors, the LEDs blink from LEDs D16 blue and D17 blue to LED D16 green continuously.
Figure 1. APB3 to AXI4 Lite Converter Core Example Design
Table 1. Trion® Example Design Implementation
FPGA LUTs Registers Memory Blocks Multipliers fMAX (MHz)1 Efinity® Version2
T20 BGA256 C4 82 53 0 0 171 2020.1
Table 2. Titanium Example Design Implementation
FPGA Logic and Adders Flip-flops Memory Blocks DSP48 Blocks fMAX (MHz)1 Efinity® Version2
Ti60 F225 C4 242 248 0 0 390 2021.2
1 Using default parameter settings.
2 Using Verilog HDL.