Features

• Complies with AMBA AXI4-Lite specification (ARM IHI 0022D) and the APB3 specification (ARM IHI 0024B)
• 32-bit slave on a 32-bit APB3 interface
• 32-bit master on a 32-bit AXI4-Lite interface
• Supports no wait write, wait write, no wait read, and wait read operations
• Verilog HDL RTL and simulation testbench
• Includes example designs targeting the Trion® T20 BGA256 Development Board and Titanium Ti60 F225 Development Board